Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture

2020 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas45731.2020.9180871 ◽

2020 ◽

Author(s):

Y. Xiong ◽

J. Zhou ◽

S. Pal ◽

D. Blaauw ◽

H. S. Kim ◽

...

Keyword(s):

Neural Network ◽

Low Power ◽

Deep Neural Network ◽

Reconfigurable Architecture

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A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2018.2880363 ◽

2019 ◽

Vol 66 (5) ◽

pp. 1794-1804 ◽

Author(s):

Donghyeon Han ◽

Jinsu Lee ◽

Jinmook Lee ◽

Hoi-Jun Yoo

Keyword(s):

Neural Network ◽

Online Learning ◽

Low Power ◽

Object Tracking ◽

Real Time ◽

Deep Neural Network

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An FPGA-based accelerator for deep neural network with novel reconfigurable architecture

IEICE Electronics Express ◽

10.1587/elex.18.20210012 ◽

2021 ◽

Vol 18 (4) ◽

pp. 20210012-20210012

Author(s):

Han Jia ◽

Daming Ren ◽

Xuecheng Zou

Keyword(s):

Neural Network ◽

Deep Neural Network ◽

Reconfigurable Architecture

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A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351398 ◽

2018 ◽

Author(s):

Donghyeon Han ◽

Jinsu Lee ◽

Jinmook Lee ◽

Sungpill Choi ◽

Hoi-Jun Yoo

Keyword(s):

Neural Network ◽

Low Power ◽

Object Tracking ◽

Real Time ◽

Mobile Devices ◽

Deep Neural Network ◽

Neural Network Training ◽

Network Training

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Design of a Low Power Bfloat16 Pipelined MAC Unit for Deep Neural Network Applications

10.1109/tensymp52854.2021.9550912 ◽

2021 ◽

Author(s):

Ankita Tiwari ◽

Gaurav Trivedi ◽

Prithwijit Guha

Keyword(s):

Neural Network ◽

Low Power ◽

Deep Neural Network ◽

Network Applications ◽

Neural Network Applications

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Low-Power Communication Method using On-Device Deep Neural Network for Low-Power Image Recognition System

The Journal of Korean Institute of Communications and Information Sciences ◽

10.7840/kics.2019.44.8.1588 ◽

2019 ◽

Vol 44 (8) ◽

pp. 1588-1596

Author(s):

Jaebong Lim ◽

Yunju Baek

Keyword(s):

Neural Network ◽

Low Power ◽

Image Recognition ◽

Deep Neural Network ◽

Recognition System ◽

Communication Method

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Hybrid Fixed-Point/Binary Deep Neural Network Design Methodology for Low-Power Object Detection

IEEE Journal on Emerging and Selected Topics in Circuits and Systems ◽

10.1109/jetcas.2020.3015753 ◽

2020 ◽

Vol 10 (3) ◽

pp. 388-400

Author(s):

Jiun-In Guo ◽

Chia-Chi Tsai ◽

Jian-Lin Zeng ◽

Shao-Wei Peng ◽

En-Chih Chang

Keyword(s):

Neural Network ◽

Fixed Point ◽

Low Power ◽

Object Detection ◽

Network Design ◽

Design Methodology ◽

Deep Neural Network

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Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network

Progresses in Artificial Intelligence and Neural Systems - Smart Innovation, Systems and Technologies ◽

10.1007/978-981-15-5093-5_8 ◽

2020 ◽

pp. 79-89

Author(s):

Erik Anzalone ◽

Maurizio Capra ◽

Riccardo Peloso ◽

Maurizio Martina ◽

Guido Masera

Keyword(s):

Neural Network ◽

Low Power ◽

Deep Neural Network ◽

Sparse Matrix ◽

Hardware Accelerator

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PRArch: Pattern-Based Reconfigurable Architecture for Deep Neural Network Acceleration

2020 IEEE 22nd International Conference on High Performance Computing and Communications; IEEE 18th International Conference on Smart City; IEEE 6th International Conference on Data Science and Systems (HPCC/SmartCity/DSS) ◽

10.1109/hpcc-smartcity-dss50907.2020.00016 ◽

2020 ◽

Author(s):

Zhaoming Jiang ◽

Zhuoran Song ◽

Xiaoyao Liang ◽

Naifeng Jing

Keyword(s):

Neural Network ◽

Deep Neural Network ◽

Reconfigurable Architecture

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Big/little deep neural network for ultra low power inference

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) ◽

10.1109/codesisss.2015.7331375 ◽

2015 ◽

Author(s):

Eunhyeok Park ◽

Dongyoung Kim ◽

Soobeom Kim ◽

Yong-Deok Kim ◽

Gunhee Kim ◽

...

Keyword(s):

Neural Network ◽

Low Power ◽

Deep Neural Network ◽

Ultra Low Power

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A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector

2018 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas.2018.8351850 ◽

2018 ◽

Author(s):

Hiroki Nakahara ◽

Tsutomu Sasao

Keyword(s):

Neural Network ◽

Low Power ◽

Deep Neural Network

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