Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes

2020 ◽  
Author(s):  
Thang Xuan Pham ◽  
Hanho Lee
Keyword(s):  
Ldpc Codes ◽  
Check Node

scholarly journals UEP Concepts in Modulation and Coding

2010 ◽  
Vol 2010 ◽  
pp. 1-14 ◽  
Author(s):  
Werner Henkel ◽  
Khaled Hassan ◽  
Neele von Deetzen ◽  
Sara Sandberg ◽  
Lucile Sassatelli ◽  
...  
Keyword(s):  
Turbo Codes ◽  
Arbitrary Number ◽  
Ldpc Codes ◽  
Unequal Error Protection ◽  
Multicarrier Modulation ◽  
Multimedia Data ◽  
Turbo Coding ◽  
Bit Loading ◽  
Check Node ◽  
Number Of Classes

First unequal error protection (UEP) proposals date back to the 1960's (Masnick and Wolf; 1967), but now with the introduction of scalable video, UEP develops to a key concept for the transport of multimedia data. The paper presents an overview of some new approaches realizing UEP properties in physical transport, especially multicarrier modulation, or with LDPC and Turbo codes. For multicarrier modulation, UEP bit-loading together with hierarchical modulation is described allowing for an arbitrary number of classes, arbitrary SNR margins between the classes, and arbitrary number of bits per class. In Turbo coding, pruning, as a counterpart of puncturing is presented for flexible bit-rate adaptations, including tables with optimized pruning patterns. Bit- and/or check-irregular LDPC codes may be designed to provide UEP to its code bits. However, irregular degree distributions alone do not ensure UEP, and other necessary properties of the parity-check matrix for providing UEP are also pointed out. Pruning is also the means for constructing variable-rate LDPC codes for UEP, especially controlling the check-node profile.

Hybrid Decoding Algorithm for LDPC Codes with Circles

2011 ◽  
Vol 271-273 ◽  
pp. 258-263
Author(s):  
Li Shuang Hu ◽  
Ming Shan Liu ◽  
Yuan Zhou ◽  
Yang Sun
Keyword(s):  
Error Rate ◽  
Belief Propagation ◽  
Additive White Gaussian Noise ◽  
Ldpc Codes ◽  
Error Correcting Codes ◽  
Parity Check ◽  
Likelihood Ratios ◽  
Decoding Algorithms ◽  
Variable Node ◽  
Check Node

At present, Low-Density Parity-Check (LDPC) codes widely used in many fields of communications have the best performance of all the Error Correcting Codes (ECC). This paper mainly studies the decoding algorithms of LDPC. It proposes an improved algorithm which is named Check-Variable nodes Hybrid(CVH) algorithm on the basis of the existing algorithms. The CVH algorithm can reduce the computational complexity during the check-node update while overcome with the correlation between the variable-node news in a code with circles. As well as, comparing with the original algorithms the performance of the new one saves 0.1 and 0.3 dB than Log-likelihood Ratios (LLR) Belief Propagation (BP) and BP - based algorithms under Additive White Gaussian Noise (AWGN) channel when the Bit Error Rate (BER) falls to through the simulation. This point shows that this algorithm can increase the decoding performance and reduce the error rate effectively.

scholarly journals Efficient high throughput decoding architecture for non-binary LDPC codes

2018 ◽  
Vol 7 (2.8) ◽  
pp. 195 ◽  
Author(s):  
C Arul Murugan ◽  
B Banuselvasaraswathy ◽  
K Gayathree ◽  
M Ishwarya Niranjana
Keyword(s):  
High Throughput ◽  
Linear Density ◽  
Ldpc Codes ◽  
Parity Check ◽  
Clock Frequency ◽  
Compression Technique ◽  
Check Node ◽  
Number Of Iterations

This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

Check Node Reliability-Based Scheduling for BP Decoding of Non-Binary LDPC Codes

2013 ◽  
Vol 61 (3) ◽  
pp. 877-885 ◽  
Author(s):  
Guojun Han ◽  
Yong Liang Guan ◽  
Xinmei Huang
Keyword(s):  
Ldpc Codes ◽  
Check Node
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