Memristive Structure-Based Chaotic System for PRNG

This paper suggests an approach to generate pseudo-random sequences based on the discrete-time model of the simple memristive chaotic system. We show that implementing Euler’s and Runge–Kutta’s methods for the simulation solutions gives the possibility of obtaining chaotic sequences that maintain general properties of the original chaotic system. A preliminary criterion based on the binary sequence balance estimation is proposed and applied to separate any binary representation of the chaotic time sequences into random and non-random parts. This gives us the possibility to delete obviously non-random sequences prior to the post-processing. The investigations were performed for arithmetic with both fixed and floating points. In both cases, the obtained sequences successfully passed the NIST SP 800-22 statistical tests. The utilization of the unidirectional asymmetric coupling of chaotic systems without full synchronization between them was suggested to increase the performance of the chaotic pseudo-random number generator (CPRNG) and avoid identical sequences on different outputs of the coupled systems. The proposed CPRNG was also implemented and tested on FPGA using Euler’s method and fixed-point arithmetic for possible usage in different applications. The FPGA implementation of CPRNG supports a generation speed up to 1.2 Gbits/s for a clock frequency of 50 MHz. In addition, we presented an example of the application of CPRNG to symmetric image encryption, but nevertheless, one is suitable for the encryption of any binary source.

Design and Implementation of Power-Efficient FSM based UART

The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

Every new generation of wireless communication standard aims to improve the overall performance and quality of service (QoS), compared to the previous generations. Increased data rates, numbers and capabilities of connected devices, new applications, and higher data volume transfers are some of the key parameters that are of interest. To satisfy these increased requirements, the synergy between wireless technologies and optical transport will dominate the 5G network topologies. This work focuses on a fundamental digital function in an orthogonal frequency-division multiplexing (OFDM) baseband transceiver architecture and aims at improving the throughput and circuit complexity of this function. Specifically, we consider the high-order QAM demodulation and apply approximation techniques to achieve our goals. We adopt approximate computing as a design strategy to exploit the error resiliency of the QAM function and deliver significant gains in terms of critical performance metrics. Particularly, we take into consideration and explore four demodulation algorithms and develop accurate floating- and fixed-point circuits in VHDL. In addition, we further explore the effects of introducing approximate arithmetic components. For our test case, we consider 64-QAM demodulators, and the results suggest that the most promising design provides bit error rates (BER) ranging from 10−1 to 10−4 for SNR 0–14 dB in terms of accuracy. Targeting a Xilinx Zynq Ultrascale+ ZCU106 (XCZU7EV) FPGA device, the approximate circuits achieve up to 98% reduction in LUT utilization, compared to the accurate floating-point model of the same algorithm, and up to a 122% increase in operating frequency. In terms of power consumption, our most efficient circuit configurations consume 0.6–1.1 W when operating at their maximum clock frequency. Our results show that if the objective is to achieve high accuracy in terms of BER, the prevailing solution is the approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency and sustains a throughput of 323 Msamples/s.

10-Bit, 1GS/S Time-Interleaved SAR ADC

This paper describes the implementation of a 4-channel, 10-bit, 1 GS/s time-interleaved analog to digital converter (TI-ADC) in 65nm CMOS technology. Each channel consists of interleaved T/H and ADC array operating at 250 MS/s, with each ADC array containing 14 timeinterleaved sub-ADCs. This configuration provides high sampling rate even though each subADC works at a moderate sampling rate. We have selected 10-bit successive approximation ADC (SAR ADC) as a sub-ADC, since this architecture is most suitable for low power and medium resolution. SAR ADC works on binary search algorithm, since it resolves 1-bit at a time. The target sampling rate was 20 MS/s in this design, however the sampling rate achieved is 15 MS/s. As a result, the 10-bit SAR ADC operates at 15 MS/s with power consumption of 560 μW at 1.2 V supply and achieves SNDR of 57 dB (i.e. ENOB 9.2 bits) near nyquist rate input. The resulting Figure of Merit (FoM) is 63.5 fJ/step. The achieved DNL and INL is +0.85\-0.9 LSB and +1\-1.1 LSB respectively. The 10-bit SAR ADC occupies an active area of 300 μm × 440 μm. The functionality of single channel TI-SAR ADC has been verified by simulation with input signal frequency of 33.2 MHz and clock frequency of 250 MHz. The desired SNDR of 59.3 dB has been achieved with power consumption of 11.6 mW. This results in a FoM value of 60 fJ/step.

INVESTIGATION OF THE ABSOLUTENESS OF TIME

In classical physics, time is considered absolute. It is believed that all processes, regardless of their complexity, do not affect the flow of time The theory of relativity determines that the flow of time for bodies depends both on the speed of movement of bodies and on the magnitude of the gravitational potential. It is believed that time in space orbit passes slower due to the high speed of the spacecraft, and faster due to the lower gravitational potential than on the surface of the Earth. Currently, the dependence of time on the magnitude of the gravitational potential and velocity (relativistic effect) is taken into account in global positioning systems. However, studying the relativistic effect, scientists have made a wrong interpretation of the difference between the clock frequency of an orbiting satellite and the clock frequency on the Earth's surface. All further studies to explain the relativistic effect were carried out according to a similar scenario, that is, only the difference in clock frequencies under conditions of different gravitational potentials was investigated. While conducting theoretical research, I found that the frequency of the signal changes along the way from the satellite to the receiver due to the influence of Earth's gravity. It was found that the readings of two high-precision clocks located at different heights will not differ after any period of time, that is, it is shown that the flow of time does not depend on the gravitational potential. It is proposed to conduct full-scale experiments, during which some high-precision clocks are sent aboard the space station, while others remain in the laboratory on the surface of the earth. It is expected that the readings of the satellite clock will be absolutely identical to the readings of the clock in the Earth laboratory.

MSPAN: A Memristive Spike-Based Computing Engine With Adaptive Neuron for Edge Arrhythmia Detection

In this work, a memristive spike-based computing in memory (CIM) system with adaptive neuron (MSPAN) is proposed to realize energy-efficient remote arrhythmia detection with high accuracy in edge devices by software and hardware co-design. A multi-layer deep integrative spiking neural network (DiSNN) is first designed with an accuracy of 93.6% in 4-class ECG classification tasks. Then a memristor-based CIM architecture and the corresponding mapping method are proposed to deploy the DiSNN. By evaluation, the overall system achieves an accuracy of over 92.25% on the MIT-BIH dataset while the area is 3.438 mm2 and the power consumption is 0.178 μJ per heartbeat at a clock frequency of 500 MHz. These results reveal that the proposed MSPAN system is promising for arrhythmia detection in edge devices.

A Low Energy Clock Network with a Huge Number of Local Synchronized Oscillators

<div>A clock system for a huge grid of small clock regions is presented. There is an oscillator in each clock region, which drives the local clock of a processing element (PE). The oscillators are kept synchronized by exploiting the phase of their neighbors. In an infinite mesh, the clock skew would be zero, but in a network of limited size there will be fringe effects. In a mesh with 25×25 oscillators, the maximum skew between neighboring regions is within 3.3 ps. By slightly adjusting the free running frequency of the oscillators, this skew can be reduced to 1.2 ps. The mesh may contain millions of clock regions.</div><div> Because there is no central clock, both power consumption and clock frequency can be improved compared to a conventional clock distribution network. A PE of 150×150 µm² running at 6.7 GHz with 93 master-slave flip-flops is used as an example. The PE-internal clock skew is less than 2.3 ps, and the energy consumption of the clock system 807 µW per PE. It corresponds to an effective gate and wire capacitance of 509 aF, or 7.3 gate capacitances.</div><div> Power noise is reduced by scheduling the local oscillators gradually along one of the grid’s axes. In this way, surge currents, which generally have their peaks at the clock edges, are distributed evenly over a full clock cycle.</div>

A Low Energy Clock Network with a Huge Number of Local Synchronized Oscillators

<div>A clock system for a huge grid of small clock regions is presented. There is an oscillator in each clock region, which drives the local clock of a processing element (PE). The oscillators are kept synchronized by exploiting the phase of their neighbors. In an infinite mesh, the clock skew would be zero, but in a network of limited size there will be fringe effects. In a mesh with 25×25 oscillators, the maximum skew between neighboring regions is within 3.3 ps. By slightly adjusting the free running frequency of the oscillators, this skew can be reduced to 1.2 ps. The mesh may contain millions of clock regions.</div><div> Because there is no central clock, both power consumption and clock frequency can be improved compared to a conventional clock distribution network. A PE of 150×150 µm² running at 6.7 GHz with 93 master-slave flip-flops is used as an example. The PE-internal clock skew is less than 2.3 ps, and the energy consumption of the clock system 807 µW per PE. It corresponds to an effective gate and wire capacitance of 509 aF, or 7.3 gate capacitances.</div><div> Power noise is reduced by scheduling the local oscillators gradually along one of the grid’s axes. In this way, surge currents, which generally have their peaks at the clock edges, are distributed evenly over a full clock cycle.</div>

Design of double ring lock ring in extensible frequency clock generator chip

With the continuous development of computer technology and the continuous improvement of interface data rate, the clock frequency has reached the demand of several gigahertz, which makes the electromagnetic interference problem very serious. Spread spectrum clock is an effective method to reduce electromagnetic interference of digital chips. Therefore, this paper designs a double-loop phase-locked loop that can spread spectrum and has strong anti-electromagnetic noise interference ability. The designed dual-loop phase-locked loop can be used in the clock generator chip. The overall structure of the circuit consists of a main loop and a secondary loop. The main loop is an adjustable phase-locked loop circuit that can provide an output with a center frequency of 500MHz. The secondary loop can realize the spread spectrum function by charging and discharging the filter capacitor of the main loop loop, and at the same time, the spreading depth can be set by the feedback based on the frequency division. The dual-loop phase-locked loop designed in this paper has a good effect in spread spectrum and anti-electromagnetic interference noise.

High Performance Reconfigurable Elliptic Curve Cipher Processor Implementation

Elliptic Curve Encryption (ECC) has been widely used in the field of digital signatures in communication security. ECC standards and the diversification of application scenarios put forward higher requirements for the flexibility of ECC processors. Therefore, it is necessary to design a flexible and reconfigurable processor to adapt to changing standards. The cryptographic processor chip designed in this paper supports the choice of prime and binary fields, supports the maximum key length of 576 bits, uses microcode programming to achieve reconfigurable function, and significantly improves the flexibility of the dedicated cryptographic processor. At the same time, the speed of modular multiplication and modular division can be greatly improved under the condition of keeping the low level of hardware resources through a carefully designed modular unit of operation. After using FPGA for hardware implementation, it is configured into a 256-bit key length. The highest clock frequency of this design can reach 55.7MHz, occupying 12425LUTS. Compared with a similar design, the performance is also greatly improved. After MALU module optimization design, modular multiplication module division also has significant advantages in computing time consumption.