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TED Thermo Electrical Designer: A New Physical Design Verification Tool
Sixth International Symposium on Quality of Electronic Design (ISQED'05)
◽
10.1109/isqed.2005.119
◽
2005
◽
Cited By ~ 2
Author(s):
E. Sokolowska
◽
M. Barszcz
◽
B. Kaminska
Keyword(s):
Physical Design
◽
Design Verification
◽
Verification Tool
Download Full-text
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Cited By
References
Geometric and Electrical Design Verification Tool for the Development of GaAs Digital ICs
IETE Technical Review
◽
10.1080/02564602.2001.11416998
◽
2001
◽
Vol 18
(6)
◽
pp. 483-486
Author(s):
Samuder Gupta
◽
Asok Bhattacharyya
Keyword(s):
Design Verification
◽
Verification Tool
Download Full-text
A Bipolar VLSI Custom Macro Physical Design Verification Strategy
IBM Journal of Research and Development
◽
10.1147/rd.264.0485
◽
1982
◽
Vol 26
(4)
◽
pp. 485-496
Author(s):
J. F. McCabe
◽
A. Z. Muszynski
Keyword(s):
Physical Design
◽
Design Verification
◽
Verification Strategy
◽
Custom Macro
Download Full-text
SOC Physical Design Verification
A Practical Approach to VLSI System on Chip (SoC) Design
◽
10.1007/978-3-030-23049-4_10
◽
2019
◽
pp. 201-214
Author(s):
Veena S. Chakravarthi
Keyword(s):
Physical Design
◽
Design Verification
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A system design verification toolfor dynamic performance of software
10.2514/6.1979-1933
◽
1979
◽
Author(s):
F. PFISTERER
Keyword(s):
System Design
◽
Dynamic Performance
◽
Design Verification
◽
Verification Tool
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Valor announces new enterprise release for DFM and physical design verification
Circuit World
◽
10.1108/cw.2001.21727dad.010
◽
2001
◽
Vol 27
(4)
◽
Keyword(s):
Physical Design
◽
Design Verification
Download Full-text
ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
◽
10.1109/iscas.2004.1329501
◽
2004
◽
Cited By ~ 1
Author(s):
Rouying Zhan
◽
Haigang Feng
◽
Haolu Xie
◽
A. Wang
Keyword(s):
Design Verification
◽
Verification Tool
◽
Esd Protection
Download Full-text
ESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2004.833613
◽
2004
◽
Vol 23
(10)
◽
pp. 1421-1428
◽
Cited By ~ 11
Author(s):
R. Zhan
◽
H. Feng
◽
Q. Wu
◽
H. Xie
◽
X. Guan
◽
...
Keyword(s):
Design Verification
◽
Verification Tool
◽
Esd Protection
Download Full-text
Multi-selection method for physical design verification applications
10.1117/12.878463
◽
2011
◽
Cited By ~ 4
Author(s):
Salma Mostafa
◽
J. Andres Torres
◽
Peter Rezk
◽
Kareem Madkour
Keyword(s):
Selection Method
◽
Physical Design
◽
Design Verification
Download Full-text
PRESSS 3: The Five-Story Precast Test Building Vol. 3-3 - Design Verification, Instrumentation &Test Procedures,
10.15554/pci.rr.seis-013
◽
2002
◽
Author(s):
Sri Sritharan
◽
Stefano Pampanin
◽
James R. Conley
Keyword(s):
Design Verification
◽
Test Procedures
Download Full-text
Physical design algorithms for asynchronous circuits
10.31274/etd-180810-5467
◽
2016
◽
Author(s):
Gang Wu
Keyword(s):
Asynchronous Circuits
◽
Physical Design
◽
Design Algorithms
Download Full-text
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