Pulse density modulation control-based multi-load handling three leg inverter for cooking applications

Purpose Induction heating applications aided by power electronic control have become very attractive in the recent past. For cooking applications, power electronics circuits are very suitable to feed power to multi loads with an appropriate control technique. The purpose of this paper is to develop a three leg inverter to feed power to three loads simultaneously and independently. Design/methodology/approach Pulse density modulation control technique is used to control the output power independently with constant switching frequency. Findings Multi-load handling converter with independent power control is achieved with reduced number of switching devices (two switches/per load) with simple control strategy. Originality/value The proposed system is simulated in MATLAB/Simulink, and the thermal analysis is carried out in COMSOL multi-physics software. The hardware realisation is performed for a 1 kW prototype with 20 kHz switching frequency and 10 kHz pulse density modulation frequency. PIC16F877A microcontroller is used to validate the experimental results for various values of control signals (DPDM). The simulation and experimental results are in good agreement and validates the developed system.

Canard-induced mixed mode oscillations as a mechanism for the Bonhoeffer-van der Pol circuit under parametric perturbation

Purpose This paper aims to investigate the singular Hopf bifurcation and mixed mode oscillations (MMOs) in the perturbed Bonhoeffer-van der Pol (BVP) circuit. There is a singular periodic orbit constructed by the switching between the stable focus and large amplitude relaxation cycles. Using a generalized fast/slow analysis, the authors show the generation mechanism of two distinct kinds of MMOs. Design/methodology/approach The parametric modulation can be used to generate complicated dynamics. The BVP circuit is constructed as an example for second-order differential equation with periodic perturbation. Then the authors draw the bifurcation parameter diagram in terms of a containing two attractive regions, i.e. the stable relaxation cycle and the stable focus. The transition mechanism and characteristic features are investigated intensively by one-fast/two-slow analysis combined with bifurcation theory. Findings Periodic perturbation can suppress nonlinear circuit dynamic to a singular periodic orbit. The combination of these small oscillations with the large amplitude oscillations that occur due to canard cycles yields such MMOs. The results connect the theory of the singular Hopf bifurcation enabling easier calculations of where the oscillations occur. Originality/value By treating the perturbation as the second slow variable, the authors obtain that the MMOs are due to the canards in a supercritical case or in a subcritical case. This study can reveal the transition mechanism for multi-time scale characteristics in perturbed circuit. The information gained from such results can be extended to periodically perturbed circuits.

A compact high gain wideband millimeter wave 1 × 2 array antenna for 26/28 GHz 5G applications

Purpose This paper aims to present the design, fabrication and analysis of a wideband, enhanced gain 1 × 2 patch antenna array with a simple profile structure to meet the desired antenna traits, such as wide bandwidth, high gain and directional patterns expected for the upcoming fifth-generation (5G) wireless applications in the millimeter wave band. To enhance these parameters (bandwidth and gain), a new antenna geometry by using a T-junction power divider is presented. Design/methodology/approach The theory behind this paper is connected with advancements in the 5G communications related to antennas. The methodology used in this work is to design a high gain array antenna and to identify the best possible power divider to deliver the power in an optimized way. The design methodology adopts several steps like the selection of proper substrate material as per the design specification, size of the antenna as per the frequency of operation and application-specific environment condition. The simulation has been performed on the designed antenna in the electromagnetic simulation tool (high-frequency structure simulator [HFSS]), and optimization has been done with parametric analysis, and then the final array antenna model is proposed. The proposed array contains 2-patch elements excited by one port adapted to 50 Ω through a T-junction power divider. The 1 × 2 array configuration with the suggested geometry helps to improve the overall gain of the antenna, and the implementation of the T-junction power divider provides enhanced bandwidth. The proposed array designed using a 1.6 mm thick flame retardant substrate occupies a compact area of 14 × 12.14 mm2. Findings The prototype of the array antenna is fabricated and measured to validate the design concept. A good agreement has been reached between the measured and simulated antenna parameters. The measured results confirm its wideband and high gain characteristics, covering 24.77–28.80 GHz for S11= –10 dB with a peak gain of about 15.16 dB at 27.65 GHz. Originality/value The proposed antenna covers the bandwidth requirements of the 26 GHz n258 band (24.25–27.50 GHz) to be deployed in the UK and Europe. The suggested antenna structure also covers the federal communications commission (FCC)-regulated 28 GHz n261 band (27.5–28.35 GHz) to be deployed in America and Canada. The low profile, compact size, simple structure, wide bandwidth, high gain and desired directional radiation patterns confirm the applicability of the suggested array antenna for the upcoming 5 G wireless systems.

A new approach for task managing in the fog-based medical cyber-physical systems using a hybrid algorithm

Purpose This paper aims to offer a hybrid genetic algorithm and the ant colony optimization (GA-ACO) algorithm for task mapping and resource management. The paper aims to reduce the makespan and total response time in fog computing- medical cyber-physical system (FC-MCPS). Design/methodology/approach Swift progress in today’s medical technologies has resulted in a new kind of health-care tool and therapy techniques like the MCPS. The MCPS is a smart and reliable mechanism of entrenched clinical equipment applied to check and manage the patients’ physiological condition. However, the extensive-delay connections among cloud data centers and medical devices are so problematic. FC has been introduced to handle these problems. It includes a group of near-user edge tools named fog points that are collaborating until executing the processing tasks, such as running applications, reducing the utilization of a momentous bulk of data and distributing the messages. Task mapping is a challenging problem for managing fog-based MCPS. As mapping is an non-deterministic pol ynomial-time-hard optimization issue, this paper has proposed a procedure depending on the hybrid GA-ACO to solve this problem in FC-MCPS. ACO and GA, that is applied in their standard formulation and combined as hybrid meta-heuristics to solve the problem. As such ACO-GA is a hybrid meta-heuristic using ACO as the main approach and GA as the local search. GA-ACO is a memetic algorithm using GA as the main approach and ACO as local search. Findings MATLAB is used to simulate the proposed method and compare it to the ACO and MACO algorithms. The experimental results have validated the improvement in makespan, which makes the method a suitable one for use in medical and real-time systems. Research limitations/implications The proposed method can achieve task mapping in FC-MCPS by attaining high efficiency, which is very significant in practice. Practical implications The proposed approach can achieve the goal of task scheduling in FC-MCPS by attaining the highest total computational efficiency, which is very significant in practice. Originality/value This research proposes a GA-ACO algorithm to solve the task mapping in FC-MCPS. It is the most significant originality of the paper.

Suitability of passive RC-network-based inductorless bridged-T as a bandpass NGD circuit

Purpose The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function. Design/methodology/approach The BP NGD topology under study is composed of an inductorless passive resistive capacitive network. The circuit analysis is elaborated from the equivalent impedance matrix. Then, the analytical model of the C-shunt bridged-T topology voltage transfer function is established. The BP NGD analysis of the considered topology is developed in function of the bridged-T parameters. The NGD properties and characterizations of the proposed topology are analytically expressed. Moreover, the relevance of the BP NGD theory is verified with the design and fabrication of surface mounted device components-based proof-of-concept (PoC). Findings From measurement results, the BP NGD network with −151 ns at the center frequency of 1 MHz over −6.6 dB attenuation is in very good agreement with the C-shunt bridged-T PoC. Originality/value This paper develops a mathematical modeling theory and measurement of a C-shunt bridged-T network circuit.

Comparative analysis of two-level and three-level multilevel inverter for electric vehicle application using BLDC motor drive

Purpose The conventional two-level inverter suffers from harmonics, higher direct current (DC) link voltage requirement, higher dv/dt and heating of the rotor. This study aims to overcome by using a multilevel inverter for brushless DC (BLDC) drive. Design/methodology/approach This paper presents a comparative analysis of the conventional two-level and three-level multilevel inverter for electric vehicle (EV) application using BLDC drive. Findings A three-level Active Neutral Point Clamped Multilevel inverter (ANPCMLI) is proposed in this paper which provides DC link voltage control. Simulation studies of the multilevel inverter and BLDC motor is carried out in MATLAB. Originality/value The ANPCMLI fed BLDC simulation results shows that there is the significant reduction in the BLDC motor torque ripple, switching stress and harmonic distortion in the BLDC motor fed ANPCMLI compared to the conventional two-level inverter. A prototype of ANPCMLI fed BLDC drive along with field programmable gate array (FPGA) control is built and MATLAB simulation results are verified experimentally.

Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC

Purpose Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library. Findings The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively. Originality/value Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.

TPTPC and BHC integrated grid connected energy storage system for power loss reduction

Purpose This paper aims to propose a bidirectional hidden converter (BHC)-based three-phase DC–AC conversion for energy storage application. BHC is the new concept to vary an energy storage device voltage into wide range. Hidden converter power loss and power rating are reduced by using zero-sequence injection-based carrier-based pulse-width modulation (CBPWM) strategy. Design/methodology/approach By using this control strategy, a BHC processes only little amount of power during double-stage conversion, mostly during direct or single-stage conversion of the three-phase three-port converter (TPTPC) only processing the maximum power. Findings TPTPC consists of two sets of positive group switches for inversion process, one set of switches is regular inverter switches called vertical positive group switches, and the second set is anti-series switches, which are horizontally connected for direct or single-stage conversion. Originality/value Characteristics, principles and implementations of proposed DC–AC 3Ø conversion system and its PWM strategy are analyzed. Through experimental outputs, the effectiveness and viability of the proposed solutions are validated.

Design of ternary subtractor using multiplexers

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

A new technique for right half plane zero elimination from dynamics of a boost converter using magnetic coupling concept

Purpose Control-signal-to-output-voltage transfer function of the conventional boost converter has at least one right-half plane zero (RHPZ) in the continuous conduction mode which can restrict the open-loop bandwidth of the converter. This problem can complicate the control design for the load voltage regulation and conversely, impact on the stability of the closed-loop system. To remove this positive zero and improve the dynamic performance, this paper aims to suggest a novel boost topology with a step-up voltage gain by developing the circuit diagram of a conventional boost converter. Design/methodology/approach Using a transformer, two different pathways are provided for a classical boost circuit. Hence, the effect of the RHPZ can be easily canceled and the voltage gain can be enhanced which provides conditions for achieving a smaller working duty cycle and reducing the voltage stress of the power switch. Using this technique makes it possible to achieve a good dynamic response compared to the classical boost converter. Findings The observations show that the phase margin of the proposed boost converter can be adequately improved, its bandwidth is largely increased, due to its minimum-phase structure through RHPZ cancellation. It is suitable for fast dynamic response applications such as micro-inverters and fuel cells. Originality/value The introduced method is analytically studied via determining the state-space model and necessary criteria are obtained to achieve a minimum-phase structure. Practical observations of a constructed prototype for the voltage conversion from 24 V to 100 V and various load conditions are shown.