Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technology

Author(s):  
K. Kawakami ◽  
T. Shiro ◽  
H. Yamasaki ◽  
K. Yoda ◽  
H. Fujimoto ◽  
...  
2015 ◽  
Vol 28 (11) ◽  
pp. 1393-1401 ◽  
Author(s):  
Alessandro Sbrizzi ◽  
Benedikt A. Poser ◽  
Desmond H. Y. Tse ◽  
Hans Hoogduin ◽  
Peter R. Luijten ◽  
...  

2000 ◽  
Vol 4 (7) ◽  
pp. 226-228 ◽  
Author(s):  
I. Ochiai ◽  
M.P.C. Fossorier ◽  
H. Imai

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