6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-Handling

2021 ◽  
Author(s):  
Aravind Nagulu ◽  
Sasank Garikapati ◽  
Mostafa Essawy ◽  
Igor Kadota ◽  
Tingjun Chen ◽  
...  
Keyword(s):  
Full Duplex ◽  
Switched Capacitor ◽  
Delay Lines ◽  
Power Handling

Parasitic-compensated switched-capacitor delay lines

1988 ◽  
Vol 24 (7) ◽  
pp. 377 ◽  
Author(s):  
V.F. Dias ◽  
J.E. Franca
Keyword(s):  
Switched Capacitor ◽  
Delay Lines

A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay-Bandwidth Limit

2021 ◽  
pp. 1-1
Author(s):  
Aravind Nagulu ◽  
Aditya Gaonkar ◽  
Sohail Ahasan ◽  
Sasank Garikapati ◽  
Tingjun Chen ◽  
...  
Keyword(s):  
Time Delay ◽  
Full Duplex ◽  
Switched Capacitor ◽  
True Time Delay ◽  
True Time
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