Interfacing UML 2.0 for Multiprocessor System-on-Chip Design Flow

2005 International Symposium on System-on-Chip ◽

10.1109/issoc.2005.1595656 ◽

2005 ◽

Author(s):

J. Riihimaki ◽

P. Kukkala ◽

T. Kangas ◽

M. Hannikainen ◽

T.D. Hamalainen

Keyword(s):

System On Chip ◽

Design Flow ◽

Multiprocessor System ◽

Chip Design ◽

Uml 2.0 ◽

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Colif: A multilevel design representation for application-specific multiprocessor system-on-chip design

Proceedings 12th International Workshop on Rapid System Prototyping. RSP 2001 ◽

10.1109/iwrsp.2001.933847 ◽

2002 ◽

Author(s):

W.O. Cesario ◽

G. Nicolescu ◽

L. Gauthier ◽

D. Lyonnard ◽

A.A. Jerraya

Keyword(s):

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

Design Representation ◽

On Chip ◽

Application Specific

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A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design

Proceedings Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2004.1269256 ◽

2004 ◽

Author(s):

F. Menichelli ◽

M. Olivieri ◽

L. Benini ◽

M. Donno ◽

L. Bisdounis

Keyword(s):

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

Architecture Exploration ◽

Simulation Based ◽

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Multiprocessor System-on-Chip Design with Fuzzy Dynamic Scheduling for Parallel Video Processing

2011 10th IEEE/ACIS International Conference on Computer and Information Science ◽

10.1109/icis.2011.19 ◽

2011 ◽

Author(s):

Da Li ◽

Yibin Hou ◽

Zhangqin Huang ◽

Chunhua Xiao

Keyword(s):

Video Processing ◽

Dynamic Scheduling ◽

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

Parallel Video Processing ◽

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System-on-Chip design flow for the image signal processor of a nonlinear CMOS imaging system

Electronic Imaging ◽

10.2352/issn.2470-1173.2019.9.imse-363 ◽

2019 ◽

Vol 2019 (9) ◽

pp. 363-1-363-7

Author(s):

Maikon Nascimento ◽

Dileepan Joseph

Keyword(s):

Imaging System ◽

System On Chip ◽

Design Flow ◽

Chip Design ◽

On Chip ◽

Image Signal Processor ◽

Signal Processor

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Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design

IEEE Transactions on Evolutionary Computation ◽

10.1109/tevc.2005.860766 ◽

2006 ◽

Vol 10 (3) ◽

pp. 358-374 ◽

Author(s):

C. Erbas ◽

S. Cerav-Erbas ◽

A.D. Pimentel

Keyword(s):

Evolutionary Algorithms ◽

Multiobjective Optimization ◽

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

Mapping Problem ◽

Application Mapping ◽

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Scalable Multistage Network for Multiprocessor System-on-Chip Design

8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05) ◽

10.1109/ispan.2005.77 ◽

2006 ◽

Author(s):

S. Meftali ◽

J.-L. Dekeyser ◽

I.D. Scherson

Keyword(s):

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

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A Distributed Architecture Model for Heterogeneous Multiprocessor System-on-Chip Design

Embedded Software and Systems - Lecture Notes in Computer Science ◽

10.1007/11535409_21 ◽

2005 ◽

pp. 150-157

Author(s):

Qiang Wu ◽

Jinian Bian ◽

Hongxi Xue

Keyword(s):

System On Chip ◽

Multiprocessor System ◽

Distributed Architecture ◽

Chip Design ◽

Architecture Model ◽

On Chip ◽

Heterogeneous Multiprocessor

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Multiprocessor system-on-chip design for industrial wireless application

2016 International Symposium on Electronics and Smart Devices (ISESD) ◽

10.1109/isesd.2016.7886692 ◽

2016 ◽

Author(s):

Nico Surantha ◽

Astri Maria ◽

Yuhei Nagao ◽

Hiroshi Ochi

Keyword(s):

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

Wireless Application ◽

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Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.96 ◽

2014 ◽

Author(s):

Bharath Phanibhushana ◽

Sandip Kundu

Keyword(s):

Network On Chip ◽

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

On Chip ◽

Heterogeneous Multiprocessor

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Performance Evaluation Methods for Multiprocessor System-on-Chip Design

Industrial Information Technology - EDA for IC System Design, Verification, and Testing ◽

10.1201/9781420007947.ch6 ◽

2006 ◽

pp. 6-1-6-14 ◽

Author(s):

Ahmed Jerraya ◽

Iuliana Bacivarov

Keyword(s):

Performance Evaluation ◽

Evaluation Methods ◽

System On Chip ◽

Multiprocessor System ◽

Chip Design ◽

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