2014 IEEE Computer Society Annual Symposium on VLSI
Latest Publications

TOTAL DOCUMENTS

121

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Published By IEEE

9781479937653, 9781479937639

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Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.47 ◽

2014 ◽

Author(s):

Tariq B. Ahmad ◽

Maciej Ciesielski

Keyword(s):

Verilog Hdl ◽

Domain Partitioning

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Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving Computation

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.86 ◽

2014 ◽

Cited By ~ 4

Author(s):

Nektarios Georgios Tsoutsos ◽

Michail Maniatakos

Keyword(s):

Privacy Preserving

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Glitch Power Reduction via Clock Skew Scheduling

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.75 ◽

2014 ◽

Cited By ~ 2

Author(s):

Arunkumar Vijayakumar ◽

Sandip Kundu

Keyword(s):

Power Reduction ◽

Clock Skew ◽

Clock Skew Scheduling

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Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.41 ◽

2014 ◽

Cited By ~ 9

Author(s):

Jiaoyan Chen ◽

Christian Spagnol ◽

Satish Grandhi ◽

Emanuel Popovici ◽

Sorin Cotofana ◽

...

Keyword(s):

Timing Analysis ◽

Delay Model ◽

Combinational Circuits

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Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.10 ◽

2014 ◽

Cited By ~ 7

Author(s):

Anirban Sengupta ◽

Vipul Kumar Mishra

Keyword(s):

Swarm Intelligence ◽

Loop Unrolling ◽

Performance Tradeoff

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High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation Arrays

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.99 ◽

2014 ◽

Author(s):

Darryl Shima ◽

Ganesh Balakrishnan

Keyword(s):

Gallium Arsenide ◽

Misfit Dislocation ◽

High Mobility ◽

Silicon Substrates ◽

Dislocation Arrays

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Organizing Committee

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.5 ◽

2014 ◽

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System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.38 ◽

2014 ◽

Cited By ~ 6

Author(s):

Santhosh Kumar Rethinagiri ◽

Oscar Palomar ◽

Javier Arias Moreno ◽

Osman Unsal ◽

Adrian Cristal ◽

...

Keyword(s):

Multimedia Applications ◽

System Level ◽

Energy Estimation ◽

Power And Energy

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A Graph-Based 3D IC Partitioning Technique

2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.82 ◽

2014 ◽

Cited By ~ 7

Author(s):

Sabyasachee Banerjee ◽

Subhashis Majumder ◽

Bhargab B. Bhattacharya

Keyword(s):

3D Ic ◽

Partitioning Technique

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2014 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2014.8 ◽

2014 ◽

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2014 IEEE Computer Society Annual Symposium on VLSI
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving Computation

Glitch Power Reduction via Clock Skew Scheduling

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff

High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation Arrays

Organizing Committee

System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms

A Graph-Based 3D IC Partitioning Technique

Table of contents

Export Citation Format

2014 IEEE Computer Society Annual Symposium on VLSILatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning

Trust No One: Thwarting "heartbleed" Attacks Using Privacy-Preserving Computation

Glitch Power Reduction via Clock Skew Scheduling

Linear Compositional Delay Model for the Timing Analysis of Sub-Powered Combinational Circuits

Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff

High Mobility n and p Channels on Gallium Arsenide and Silicon Substrates Using Interfacial Misfit Dislocation Arrays

Organizing Committee

System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms

A Graph-Based 3D IC Partitioning Technique

Table of contents

2014 IEEE Computer Society Annual Symposium on VLSI
Latest Publications