Genetically engineered tri-band microstrip antenna with improved directivity for mm-wave wireless application

<abstract><p>Multi-band microstrip patch antennas are convenient for mm-wave wireless applications due to their low profile, less weight, and planar structure. This paper investigates patch geometry optimization of a single microstrip antenna by employing a binary coded genetic algorithm to attain triple band frequency operation for wireless network application. The algorithm iteratively creates new models of patch surface, evaluates the fitness function of each individual ranking them and generates the next set of offsprings. Finally, the fittest individual antenna model is returned. Genetically engineered antenna was simulated in ANSYS HFSS software and compared with the non-optimized reference antenna with the same dimensions. The optimized antenna operates at three frequency bands centered at 28 GHz, 40 GHz, and 47 GHz whereas the reference antenna operates only at 28 GHz with a directivity of 6.8 dB. Further, the test result exhibits broadside radiation patterns with peak directivities of 7.7 dB, 12.1 dB, and 8.2 dB respectively. The covered impedance bandwidths when S₁₁$ \leq $-10 dB are 1.8 %, 5.5 % and 0.85 % respectively.</p></abstract>

Assertion Driven Modified Booth Encoding and Post Computation Model for Speed MAC Applications

The Multiply-Accumulate Unit (MAC) is the core computational block in many DSP and wireless application but comes with more complicated architectures. Moreover the MAC block also decides the energy consumption and the performance of the overall design; due to its lies in the maximal path delay critical propagation. Developing high performance and energy optimized MAC core is essential to optimized DSP core. In this work, a high speed and low power signed booth radix enabled MAC Unit is proposed with highly configurable assertion driven modified booth algorithm (AD-MBE). The proposed booth core is based on core optimized booth radix-4 with hierarchical partial product accumulation design and associated path delay optimization and computational complexity reduction. Here all booth generated partial products are added as post summation adder network which consists of carry select adder (CSA) & carry look ahead (CLA) sequentially which narrow down the energy and computational complexity. Here increasing the operating frequency is achieved by accumulating encoding bits of each of the input operand into assertion unit before generating end results instead of going through the entire partial product accumulation. The FPGA implementation of the proposed signed asserted booth radix-4 based MAC shows significant complexity reduction with improved system performance as compared to the conventional booth unit and conventional array multiplier.