SMT-based Contention-Free Task Mapping and Scheduling on SMART NoC

2021 ◽  
pp. 1-1
Author(s):  
Daeyeal Lee ◽  
Bill Lin ◽  
Chung-Kuan Cheng
Keyword(s):  
2011 ◽  
Vol 2011 ◽  
pp. 1-16 ◽  
Author(s):  
Diana Göhringer ◽  
Michael Hübner ◽  
Etienne Nguepi Zeutebouo ◽  
Jürgen Becker

Operating systems traditionally handle the task scheduling of one or more application instances on processor-like hardware architectures. RAMPSoC, a novel runtime adaptive multiprocessor System-on-Chip, exploits the dynamic reconfiguration on FPGAs to generate, start and terminate hardware and software tasks. The hardware tasks have to be transferred to the reconfigurable hardware via a configuration access port. The software tasks can be loaded into the local memory of the respective IP core either via the configuration access port or via the on-chip communication infrastructure (e.g. a Network-on-Chip). Recent-series of Xilinx FPGAs, such as Virtex-5, provide two Internal Configuration Access Ports, which cannot be accessed simultaneously. To prevent conflicts, the access to these ports as well as the hardware resource management needs to be controlled, e.g. by a special-purpose operating system running on an embedded processor. For that purpose and to handle the relations between temporally and spatially scheduled operations, the novel approach of an operating system is of high importance. This special purpose operating system, called CAP-OS (Configuration Access Port-Operating System), which will be presented in this paper, supports the clients using the configuration port with the services of priority-based access scheduling, hardware task mapping and resource management.


IEEE Access ◽  
2018 ◽  
Vol 6 ◽  
pp. 75110-75123 ◽  
Author(s):  
Haider Ali ◽  
Umair Ullah Tariq ◽  
Yongjun Zheng ◽  
Xiaojun Zhai ◽  
Lu Liu

2007 ◽  
pp. 347-370
Author(s):  
Zhiyuan Li ◽  
Cheng Wang
Keyword(s):  

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