Asynchronous clock generator for a 14-bit two-stage pipelined SAR ADC in 0.18 μm CMOS

2016 IEEE Nordic Circuits and Systems Conference (NORCAS) ◽

10.1109/norchip.2016.7792910 ◽

2016 ◽

Author(s):

Kairang Chen ◽

Martin Nielsen-Lonn ◽

Atila Alvandpour

Keyword(s):

Sar Adc ◽

Clock Generator ◽

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A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18µm CMOS

Microelectronics Journal ◽

10.1016/j.mejo.2016.09.002 ◽

2016 ◽

Vol 57 ◽

pp. 26-33 ◽

Author(s):

Yi Shen ◽

Shubin Liu ◽

Zhangming Zhu

Keyword(s):

Sar Adc ◽

Two Stage ◽

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An 11-bit 350MS/s 2b/cycle-Assisted SAR ADC with Improved Comparator Clock Generator

2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2018.8565710 ◽

2018 ◽

Author(s):

Shuai Li ◽

Yong-Zhen Chen ◽

Fan Ye ◽

Jun-Yan Ren

Keyword(s):

Sar Adc ◽

Clock Generator

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A Configurable Noise-Shaping Band-Pass SAR ADC With Two-Stage Clock-Controlled Amplifier

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2020.3012998 ◽

2020 ◽

Vol 67 (11) ◽

pp. 3728-3739

Author(s):

Zihao Jiao ◽

Yang Chen ◽

Xiaobo Su ◽

Quan Sun ◽

Xiaofei Wang ◽

...

Keyword(s):

Sar Adc ◽

Noise Shaping ◽

Two Stage ◽

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A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2015.7282061 ◽

2015 ◽

Author(s):

Xuan Li ◽

Shuo Huang ◽

Jianjun Zhou ◽

Xiaoyong Li

Keyword(s):

Internal Clock ◽

Sar Adc ◽

Clock Generator

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A 40nm 50S/s–8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

2011 Proceedings of the ESSCIRC (ESSCIRC) ◽

10.1109/esscirc.2011.6045009 ◽

2011 ◽

Author(s):

Ryota Sekimoto ◽

Akira Shikata ◽

Tadahiro Kuroda ◽

Hiroki Ishikuro

Keyword(s):

Low Voltage ◽

Sar Adc ◽

Clock Generator

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An asynchronous SAR ADC with gate-controlled ring oscillator for multi-phase clock generator

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) ◽

10.1109/icsict.2014.7021295 ◽

2014 ◽

Author(s):

Jifang Wu ◽

Fule Li ◽

Chun Zhang

Keyword(s):

Sar Adc ◽

Ring Oscillator ◽

Clock Generator ◽

Phase Clock ◽

Asynchronous Sar ◽

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A 348μW 68.8dB-SNDR 20MS/s Pipelined SAR ADC with a Closed-Loop Two-Stage Dynamic Amplifier

IEEE Solid-State Circuits Letters ◽

10.1109/lssc.2021.3114318 ◽

2021 ◽

pp. 1-1

Author(s):

Yigi Kwon ◽

Taewoong Kim ◽

Nan Sun ◽

Youngcheol Chae

Keyword(s):

Closed Loop ◽

Sar Adc ◽

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A 10-phases programmable clock generator for the application in control of SAR ADC realized in the CMOS 130 nm technology

2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems ◽

10.1109/mixdes.2016.7529713 ◽

2016 ◽

Author(s):

Rafal Dlugosz ◽

Tomasz Talaska

Keyword(s):

Sar Adc ◽

Clock Generator

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Design of Two-Stage Fully-Differential Driver in SAR ADC with Indirect Feedback Compensation Technique

2021 International Symposium on Devices, Circuits and Systems (ISDCS) ◽

10.1109/isdcs52006.2021.9397898 ◽

2021 ◽

Author(s):

Urbashi Basumata ◽

Annapurna Mondal ◽

Subhajit Das ◽

Hafizur Rahaman

Keyword(s):

Sar Adc ◽

Two Stage ◽

Fully Differential ◽

Feedback Compensation ◽

Compensation Technique ◽

Indirect Feedback

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A 99.8% Energy-Reduced Two-Stage Mixed Switching Scheme for SAR ADC Without Reset Energy

Circuits Systems and Signal Processing ◽

10.1007/s00034-019-01151-9 ◽

2019 ◽

Vol 38 (12) ◽

pp. 5426-5447 ◽

Author(s):

Yushi Chen ◽

Yiqi Zhuang ◽

Hualian Tang

Keyword(s):

Sar Adc ◽

Switching Scheme ◽

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