A Ka-Band Asymmetric Dual Input CMOS SOI Doherty Power Amplifier with 25 dBm Output Power and High Back-Off Efficiency

Author(s):  
Narek Rostomyan ◽  
Mustafa Ozen ◽  
Peter Asbeck
Sensors ◽  
2020 ◽  
Vol 20 (19) ◽  
pp. 5581
Author(s):  
Zhiwei Zhang ◽  
Zhiqun Cheng ◽  
Guohua Liu

This paper presents a new method to design a Doherty power amplifier (DPA) with a large, high-efficiency range for 5G communication. This is through analyzing the drain-to-source capacitance (CDS) of DPAs, and adopting appropriate impedance of the peak device. A closed design process is proposed, to design the extended efficiency range DPA based on derived theories. For validation, a DPA with large efficiency range was designed and fabricated by using two equal devices. The measured results showed that the saturated output power was between 43.4 dBm and 43.7 dBm in the target band. Around 70% saturated drain efficiency is obtained with a gain of greater than 11 dB. Moreover, the obtained drain efficiency is larger than 50% at the 10 dB power back-off, when operating at 3.5 GHz. These superior performances illustrate that the implemented DPA can be applied well in 5G communication.


Author(s):  
Alexis Courty ◽  
Pierre Medrel ◽  
Tibault Reveyrand ◽  
Philippe Bouysse ◽  
Jean-Michel Nébus ◽  
...  

Abstract This paper presents a theoretical and experimental analysis of the capabilities of the dual-input Doherty power amplifier (DPA) architecture to mitigate efficiency and output power degradations when used in a mismatched load environment. Following a simplified linear piecewise approach, an analytical demonstration is proposed to derive optimal radio frequency drives applied to the Auxiliary path of the DPA to restore power performances while avoiding large signal voltage clipping of active cells. The proposed analytical study is corroborated with harmonic balance simulated results of a C-band, 20-W GaN DPA prototype. The fabricated dual-input DPA prototype has been measured under 1.5-VSWR mismatch configurations to validate the proposed analysis.


Author(s):  
Mussa Mabrok ◽  
Zahriladha Zakaria ◽  
Tole Sutikno

Doherty power amplifier (DPA) with high efficiency at the output power back off is highly demanded for modern wireless communication systems to achieve high data rates and reduce the power consumption and operation costs. This paper presents a new design strategy for enhancing DPA’s back-off efficiency. New design strategy called asymmetrical matching network is used to achieve asymmetric operation, which helps to compensate for the low power delivered by the peaking stage in the conventional DPA. The simulation results showed an enhancement in the back-off efficiency, where the proposed design is able toachieve 46-52% drain efficiency at 8 dB output power back-off while maintains high efficiency of 73-80 % at saturation over the designed bandwidth of 3.4-3.6 GHz. The proposed design is suitable for high efficiency sub-6 GHz fifth-generation wireless applications.<br /><div> </div>


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