scholarly journals Design margin elimination through robust timing error detection at ultra-low voltage

Author(s):  
Hans Reyserhove ◽  
Wim Dehaene
2019 ◽  
Vol 16 (11) ◽  
pp. 20190180-20190180
Author(s):  
Jongeun Koo ◽  
Eunhyeok Park ◽  
Dongyoung Kim ◽  
Junki Park ◽  
Sungju Ryu ◽  
...  

2015 ◽  
Vol 5 (2) ◽  
pp. 57-68
Author(s):  
Markus Hiienkari ◽  
Jukka Teittinen ◽  
Lauri Koskinen ◽  
Matthew Turnquist ◽  
Jani Mäkipää ◽  
...  

2021 ◽  
Author(s):  
Mehdi Safarpour

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.


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