Algorithm Level Error Detection in Low Voltage Systolic Array

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

Algorithm Level Error Detection in Low Voltage Systolic Array

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

Algorithm Level Error Detection in Low Voltage Systolic Array

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

Energy-efficient technologies and architectural education

The article deals with the methodology of forming the ecological thinking of bachelor-architects, at the level of interdisciplinary relations, by introducing topics and sections on energy efficiency in the disciplines of general humanitarian, technical and artistic-compositional training. The program of step-by-step implementation of energy-efficient technologies in course design is proposed. It is aimed at bringing it closer to the current design requirements by consistently disclosing the principles of energy – efficient architecture-starting from simpler, «basic» concepts to more «specialized» ones.