Entropy considerations in improved circuits for a biologically-inspired random pulse computer

We present five novel or modified circuits intended for building a universal computer based on random pulse computing (RPC) paradigm, a biologically-inspired way of computation in which variable is represented by a frequency of a random pulse train (RPT) rather than by a logic state. For the first time we investigate operation of RPC circuits from the point of entropy. In particular, we introduce entropy budget criterion (EBC) to reliably predict whether it is even possible to create a deterministic circuit for a given mathematical operation and show its relevance to numerical precision of calculations. Based on insights gained from the EBC, unlike in the previous art, where randomness is obtained from electronics noise or a pseudorandom shift register while processing circuitry is deterministic, in our approach both variable generation and signal processing rely on the random flip-flop (RFF) whose randomness is derived from a fundamentally random quantum process. This approach offers an advantage in higher precision, better randomness of the output and conceptual simplicity of circuits.

Circuit Techniques in GaN Technology for High-Temperature Environments

As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilling. More than 15 integrated circuits were implemented and tested. We performed the HT characterization of passive elements integrated in GaN500 including resistors, capacitors, and inductors up to 600 °C. Moreover, we developed for the first time several digital circuits based on GaN500 technology, including logic gates (NOT, NAND, NOR), ring oscillators, D Flip-Flop, Delay circuits, and voltage reference circuits. The tested circuits are fabricated on a 4 mm × 4 mm chip to validate their functionality over a wide range of temperatures. The logic gates show functionality at HT over 400 °C, while the voltage reference circuits remain stable up to 550 °C.

Phospholipid Scrambling by G Protein–Coupled Receptors

Rapid flip-flop of phospholipids across the two leaflets of biological membranes is crucial for many aspects of cellular life. The transport proteins that facilitate this process are classified as pump-like flippases and floppases and channel-like scramblases. Unexpectedly, Class A G protein–coupled receptors (GPCRs), a large class of signaling proteins exemplified by the visual receptor rhodopsin and its apoprotein opsin, are constitutively active as scramblases in vitro. In liposomes, opsin scrambles lipids at a unitary rate of >100,000 per second. Atomistic molecular dynamics simulations of opsin in a lipid membrane reveal conformational transitions that expose a polar groove between transmembrane helices 6 and 7. This groove enables transbilayer lipid movement, conceptualized as the swiping of a credit card (lipid) through a card reader (GPCR). Conformational changes that facilitate scrambling are distinct from those associated with GPCR signaling. In this review, we discuss the physiological significance of GPCR scramblase activity and the modes of its regulation in cells. Expected final online publication date for the Annual Review of Biophysics, Volume 51 is May 2022. Please see http://www.annualreviews.org/page/journal/pubdates for revised estimates.

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.