MCS: Buffered Clos-network switch with in-sequence packet forwarding

Author(s):  
Ziqian Dong ◽  
Roberto Rojas-Cessa
2019 ◽  
Vol 8 (3) ◽  
pp. 5603-5608 ◽  

SDN features are making it more popular day by day: centralized monitoring, control of network equipments, increased performance and flexibility in designing network policies as per organization requirements. The SDN controller deals with data & control plane separately. The SDN switches are simply data forwarding devices and controller decides control over forwarding data through them. Controller has a technique to identify the network switch and router nodes; but it does not identify the presence of hosts before they generated network traffic and is not able to create the packet forwarding rules, security policies. The objective of this paper is to detect connected host before they generate any traffic and store host details at controller level for future researches in area of development of new network tools, applications, optimizations techniques and security. Here, we propose Instant Detection of Host in SDN (IDH-SDN) to detect host before transmission of any data packet and store host details in a HostTable at controller level. In our experiment, various network topologies have been used to test host detection and data collection algorithm and results of all experiments verified with Wireshark network packet analyzer. The HostTable data may be used for various purposes such as development of new network tools, policies, security approaches in OpenFlow network.


2019 ◽  
Vol 27 (2) ◽  
pp. 467-476 ◽  
Author(s):  
Oladele Theophilus Sule ◽  
Roberto Rojas-Cessa ◽  
Ziqian Dong ◽  
Chuan-Bi Lin

2006 ◽  
Vol 15 (02) ◽  
pp. 263-276 ◽  
Author(s):  
MOO-KYUNG KANG ◽  
CHONG-MIN KYUNG

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue does not completely remove the blocking in the buffered modules under multi-class traffic. In this paper, we propose a competition-free memory–memory–memory (CFM3) switch which is a three-stage Clos-network switch with buffered center stage. The CFM3 deploys buffered modules in all stages to simplify communication between stages. To reduce the blocking, each module is equipped with a set of buffers fully separated according to the destinations, classes of packets and the input ports of the module. Despite the buffered center stage, CFM3 is free from reordering problem due to simple control mechanism. Simulation result shows the delay of the proposed CFM3 switch closely approaches that of the ideal Output Queued switch under multi-class traffic when strict priority policy popularly used for class-based switch is deployed. The CFM3 achieves 100% throughput under uniformly distributed four-class traffic with strict priority policy while traditional MSM switch records about 77% throughput.


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