Parallel architecture for video processing in a smart camera system

Author(s):  
T. Lv ◽  
B. Ozer ◽  
W. Wolf
Sensors ◽  
2021 ◽  
Vol 21 (9) ◽  
pp. 2958
Author(s):  
Antonio Carlos Cob-Parro ◽  
Cristina Losada-Gutiérrez ◽  
Marta Marrón-Romera ◽  
Alfredo Gardel-Vicente ◽  
Ignacio Bravo-Muñoz

New processing methods based on artificial intelligence (AI) and deep learning are replacing traditional computer vision algorithms. The more advanced systems can process huge amounts of data in large computing facilities. In contrast, this paper presents a smart video surveillance system executing AI algorithms in low power consumption embedded devices. The computer vision algorithm, typical for surveillance applications, aims to detect, count and track people’s movements in the area. This application requires a distributed smart camera system. The proposed AI application allows detecting people in the surveillance area using a MobileNet-SSD architecture. In addition, using a robust Kalman filter bank, the algorithm can keep track of people in the video also providing people counting information. The detection results are excellent considering the constraints imposed on the process. The selected architecture for the edge node is based on a UpSquared2 device that includes a vision processor unit (VPU) capable of accelerating the AI CNN inference. The results section provides information about the image processing time when multiple video cameras are connected to the same edge node, people detection precision and recall curves, and the energy consumption of the system. The discussion of results shows the usefulness of deploying this smart camera node throughout a distributed surveillance system.


Author(s):  
Paula Ramos-Giraldo ◽  
S. Chris Reberg-Horton ◽  
Steven Mirsky ◽  
Edgar Lobaton ◽  
Anna M. Locke ◽  
...  

2011 ◽  
Vol 403-408 ◽  
pp. 516-521 ◽  
Author(s):  
Sanjay Singh ◽  
Srinivasa Murali Dunga ◽  
AS Mandal ◽  
Chandra Shekhar ◽  
Santanu Chaudhury

In any remote surveillance scenario, smart cameras have to take intelligent decisions to generate summary frames to minimize communication and processing overhead. Video summary generation, in the context of smart camera, is the process of merging the information from multiple frames. A summary generation scheme based on clustering based change detection algorithm has been implemented in our smart camera system for generating frames to deliver requisite information. In this paper we propose an embedded platform based framework for implementing summary generation scheme using HW-SW Co-Design based methodology. The complete system is implemented on Xilinx XUP Virtex-II Pro FPGA board. The overall algorithm is running on PowerPC405 and some of the blocks which are computationally intensive and more frequently called are implemented in hardware using VHDL. The system is designed using Xilinx Embedded Design Kit (EDK).


Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.


1996 ◽  
Author(s):  
Regina M. Mudra ◽  
M. Thaler ◽  
Gerhard Troester
Keyword(s):  

2019 ◽  
Vol 8 (1) ◽  
pp. 223-230
Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek

Video processing is an additional system that can improve the functionality of video surveillance. Integration of a simple video processing system into a complete camera system with a field-programmable gate array (FPGA) is an important step for research, to further improve the tracking process. This paper presents the integration of greyscale conversion into a complete camera system using Nios II software build tools for Eclipse. The camera system architecture is designed using the Nios II soft-core embedded processor from Altera. The proposed greyscale conversion system is designed using the C programming language in Eclipse. Parts of the architecture design in the camera system are important if greyscale conversion is to take place in the processing, such as synchronous dynamic random-access memory (SDRAM) and a video decoder driver. The image or video is captured using a Terasic TRDB-D5M camera and the data are converted to RGB format using the video decoder driver. The converted data are shown in binary format and the greyscale conversion system extracts and processes the data. The processed data are stored in the SDRAM before being sent to a VGA monitor. The camera system and greyscale conversion system were developed using the Altera DE2-70 development platform. The data from the video decoder driver and SDRAM were examined to confirm that the data conversion matched greyscale conversion formulae. The converted data in the SDRAM correctly displayed the greyscale image on a VGA monitor.


Author(s):  
Ravi Teja Nallapu ◽  
Aaditya Ravindran ◽  
Himangshu Kalita ◽  
Vishnu Reddy ◽  
Roberto Furfaro ◽  
...  
Keyword(s):  

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