Reducing Buffering Delay Using Memory Arbitration Mechanism for IPTV Based Applications

High-speed communication needs high data transfer capacity and low latency, which are the key parameters of high-speed communication. Converging different applications such as IPTV to high-speed networks requires high transmission capacity and low delay with good QoS. Delays related to IPTV are video buffering, synchronization, and switching delay that obstructs the client's excellent quality assistance. In an application like IPTV, the video signals are buffered (happened to be in near end routers), and they are recombined for the client when it is asserted. To achieve the above stated, memory banks are deployed in a set top box that is used to buffer the video signals that enter in, thereby reducing expected delay. Playback mechanism is also included along with the proposed model to accomplish a better outcome. Proposed RTL schematic design was simulated using Verilog, executed in Model Sim – Altera 10.1b (Quartus II 12.1 edition) and Cadence 5.

ISODATA SOPC-FPGA implementation of image segmentation using NIOS-II processor

<p>This paper presents an FPGA image segmentation-binarization system based on<em> </em>Iterative Self Organizing DATA <em>(ISODATA)</em> threshold using histogram analysis for embedded systems. The histogram module computes pixels levels statistics which are used by the ISODATA algorithm module to determine the segmentation threshold. In our case, this threshold binarizes a gray-scale image into two values 0 or 255. The prototype of the complete system uses an ALTERA CYCLONE-II DE2 kit with a lot of component and interfaces, such as the SD-CARD reader or a camera to read the image to be segmented, the FPGA which will implement the intellectual property (IP) core calculation with the NIOS processor, the VGA interface to view the results, and possibly of the ETHERNET interface for data transfer via internet. The use of FPGA contains the ISODATA, histogram, NIOS processor and others custom altera IPs hardware modules greatly improves processing speed and allows the binarization application to be embedded on a single chip. For the project elaboration, we have used QUARTUS-II software for the hardware development part with VHDL description, SOPC-builder or QSYS for the integration of NIOS-system, and NIOS-II-STB-ECLIPSE for the software program with eclipse c++ langage.</p><p> </p>

High speed modified carry save adder using a structure of multiplexers

Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.

Improving Performance of a Multi-Bit Arithmetic Logic Unit

In modern microprocessors to reduce the time resources the arithmetic-logic units (ALU) with an increased organization of arithmetic carry, characterized by high speed, compared to ALU with sequential organization of the arithmetic carry, are commonly used. However, while increasing the bit number of the input operands, the operating time of ALU of ALU with the accelerated arithmetic carry increases linearly depending on the number of bits. Therefore, the development of ALU, providing higher performance than the existing known solutions, is an actual task. In this work the analysis of ALU with sequential and accelerated organization of the arithmetic carry has been performed. To increase the speed of the operation, a multi-bit ALU has been developed. The simulation of ALU circuits has been executed in Altera Quartus –II CAD environment. The comparison has been performed by the number of logical elements and the maximum delay as a result of modeling the ALU circuits for 4, 8, 16, 32, and 64 bits. A scheme for checking the results has been implemented to confirm the reliability of developed ALU. As a result, it has been found that when performing operations with the 64-bit operands, the developed ALU reduces the maximum delay by 53 % compared to ALU with sequential arithmetic carry and by 35.5 % compared to ALU with the accelerated arithmetic carry, respectively.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

Improved Sampling in Carrier-Based Discountinuous SVPWM Simulation

In this study, a circuit was designed to improve sampling in discontinuous SVPWM simulations using Quartus II software. The v_beta_sin unit was successfully simulated using the waveform editor. The results displayed are in accordance with previous calculations, if the input is 000000001 then the output is 100000011 and so on. The v_alfa_cos unit is also successfully simulated using the waveform editor. The simulation results if the input is 000000001 then the output is 111111111 and so on, according to the previous calculation. The unit counter was successfully simulated using the block diagram in Quartus II. The output of this unit counter is in the form of 9 bits to retrieve v_beta_sin and v_alfa_cos data. The v_beta_sin, v_alfa_cos and counter units used as reference signals are successfully simulated and can be used as a supporting circuit in the simulation of the discontinuous SVPWM method. The results of the simulation show an increase in sampling or sampling by 512.

Development of Information-Control Interface for Communication of Spacecraft Units

Представлена разработка протокола простой и надежной передачи данных для блока управления антенной в жестких условиях эксплуатации. Логический уровень протокола реализован на ПЛИС на базе протокола HDLC. Физическая линия передачи данных представляет резервированный, гальваноразвязанный интерфейс с биполярным самосинхронизирующимся кодом Manchester-II.Актуальность разработки протокола обусловлена внедрением отечественной элементной базы, устойчивой к жестким воздействиям окружающей среды, в том числе и радиации, и степенью важности развития космической отрасли в целом, а также сфер, зависящих от нее.Рассмотрено назначение блока управления антенной. Обоснована необходимость разработки протокола информационно-управляющего сопряжения для блока управления. Проведен обзор научно-технической информации о составляющих данного протокола. Рассмотрены физический, канальный и информационный уровни разработанного протокола, а также представлена реализация канального и информационного уровня на языке Verilog HDL для ПЛИС.В программе Quartus-II разработан программный код, который реализует канальный и информационный уровни передачи данных на основе протокола информационно-управляющего сопряжения блока управления антенной с блоком-вычислителем. После чего из отдельных блоков кода формируется схемотехнический проект, где для блоков задаются входные и выходные сигналы.Моделирование протокола передачи данных проведено в среде для отладки ModelSim-Altera, а также на отработочной плате. Моделирование подтвердило правильность выбранных решений в процессе создания протокола передачи данных. На заданную команду получена верная ответная квитанция с двумя байтами контрольной суммы. Переданные данные равны принятым данным, и контрольная сумма при приеме и передаче равны друг другу.Материал, представленный в данной научной статье, может быть принят разработчиками за основу реализации обмена данными между техническими устройствами, для которых остро стоит вопрос экономии ресурсов ПЛИС.

Implementación digital basada en FPGA de la técnica PWM para el inversor multinivel en cascada

El desarrollo de topologías de inversores multiniveles ha dado lugar a diversas técnicas de modulación de ancho de pulso, entre las más utilizadas están las que utilizan señales portadoras múltiples. Sin embargo, el inconveniente de la aplicación de este tipo de técnicas de modulación es que es necesario generar un gran número de señales de conmutación para todos los dispositivos de semiconductores de potencia que componen el inversor. Los conjuntos de puertas programables en el campo son una herramienta poderosa que permite obtener estas señales de manera rápida y precisa. El propósito de este artículo es describir la metodología utilizada para generar digitalmente las señales de conmutación para un inversor multinivel utilizando una tarjeta de desarrollo tipo “arreglo de campos de compuertas programable”. El procedimiento utilizado se divide en dos programas: un script Matlab y un código creado en Quartus II. El proceso de diseño presentado es fácil, rápido, flexible y aplicable a otras técnicas de modulación multiportadora. La técnica de modulación implementada en la tarjeta de desarrollo y se verifica experimentalmente en un inversor multinivel en cascada trifásico para generar cinco niveles de tensión de salida con diferentes velocidades de modulación. Los resultados obtenidos experimentalmente se comparan con los obtenidos en la simulación con el software PSpice. El análisis de los resultados permite comprobar el correcto funcionamiento de la técnica de modulación aplicada