scholarly journals Implementation of a camera system using nios II on the altera DE2-70 board

2019 ◽  
Vol 14 (2) ◽  
pp. 513
Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek
Keyword(s):  
Video Processing ◽  
Random Access ◽  
Camera System ◽  
Embedded Processor ◽  
Nios Ii ◽  
Development Platform ◽  
Quartus Ii ◽  
Field Programmable ◽  
Sdram Controller ◽  
Recorded Image

The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor.

scholarly journals SOC integration for video processing application

2019 ◽  
Vol 8 (1) ◽  
pp. 223-230
Author(s):  
Chan Boon Cheng ◽  
Asral Bahari Jambek
Keyword(s):  
Video Processing ◽  
Random Access ◽  
Processing System ◽  
Data Conversion ◽  
Camera System ◽  
Processing Application ◽  
Video Decoder ◽  
Nios Ii ◽  
Development Platform ◽  
Conversion System

Video processing is an additional system that can improve the functionality of video surveillance. Integration of a simple video processing system into a complete camera system with a field-programmable gate array (FPGA) is an important step for research, to further improve the tracking process. This paper presents the integration of greyscale conversion into a complete camera system using Nios II software build tools for Eclipse. The camera system architecture is designed using the Nios II soft-core embedded processor from Altera. The proposed greyscale conversion system is designed using the C programming language in Eclipse. Parts of the architecture design in the camera system are important if greyscale conversion is to take place in the processing, such as synchronous dynamic random-access memory (SDRAM) and a video decoder driver. The image or video is captured using a Terasic TRDB-D5M camera and the data are converted to RGB format using the video decoder driver. The converted data are shown in binary format and the greyscale conversion system extracts and processes the data. The processed data are stored in the SDRAM before being sent to a VGA monitor. The camera system and greyscale conversion system were developed using the Altera DE2-70 development platform. The data from the video decoder driver and SDRAM were examined to confirm that the data conversion matched greyscale conversion formulae. The converted data in the SDRAM correctly displayed the greyscale image on a VGA monitor.

scholarly journals Projeto de arquitetura de um filtro para processamento de imagens utilizando processador nios ii e field programmable gate array (FPGA)

2016 ◽  
pp. 132
Author(s):  
Carlos Caetano Almeida ◽  
Danilo Pagano ◽  
Vornei Augusto Grella ◽  
Frank Alexis Canahuire Cabello ◽  
Alexandre Tomazati Oliveira ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Nios Ii ◽  
Quartus Ii ◽  
Field Programmable ◽  
Gate Array

O uso de Field Programmable Gate Array (FPGA) em sistemas embarcados permite combinar a flexibilidade do software com a velocidade do hardware, no que se chama de computação reconfigurável, podendo implementar desde processamentos simples, até circuitos como controlador de vídeo, incluindo memória RAM ou ainda incorporar processamentos complexos e exigentes computacionalmente. O projeto de desenvolvimento do circuito desejado em FPGA pode ser desenvolvido através do programa Quartus II da Altera, que permite o desenvolvimento dos circuitos eletrônicos. A programação do circuito lógico projetado é transferida para o FPGA, através de cabo USB, após recebido e carregado, o FPGA realiza as funções programadas, sendo essa programação volátil, ou seja, o dispositivo deve ser reprogramado a cada vez que é ligado. A transferência pode ser eliminada com a utilização de uma memória ROM programável ou um disco de estado sólido, o que possibilita que o projeto seja diretamente carregado para o FPGA quando ligado. Este trabalho apresenta uma arquitetura para o processamento digital de sinais através de dispositivos implementados em hardware por meio de redes de convolução (ConvNets), são redes com múltiplas camadas, que implementam filtros de convolução. No processamento de imagens, os algoritmos são em geral implementados em software e assim o desempenho computacional pode não ser adequado ou não atender requisitos de aplicações em tempo real. Nesse caso a convolução 2D pode ser aplicada de forma concorrente e/ou paralela, o que pode ser conseguido explorando-se o potencial dos FPGA’s através das ConvNets, obtendo-se assim desempenho potencialmente muito superior.

scholarly journals The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Line Drawing ◽  
Cmos Process ◽  
Embedded Processor ◽  
Processor Core ◽  
Field Programmable ◽  
The Embedded System ◽  
Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

A Novel HBE-MCM-Based Multiplier Architecture for 8-Point DCT Structure

2016 ◽  
Vol 26 (04) ◽  
pp. 1750054
Author(s):  
M. Kiruba ◽  
V. Sumathy
Keyword(s):  
Video Processing ◽  
Power Dissipation ◽  
Field Programmable Gate Array ◽  
Video Codec ◽  
Floating Point ◽  
Data Path ◽  
Image And Video Processing ◽  
Field Programmable ◽  
Minimum Number ◽  
Code Language

The Discrete Cosine Transform (DCT) structure plays a significant role in the signal processing applications such as image and video processing applications. In the traditional hardware design, the 8-point DCT architecture contains more number of logical slices in it. Also, it consists of number of multipliers to update the weight. This leads to huge area consumption and power dissipation in that architecture. To mitigate the conventional drawbacks, this paper presents a novel Hierarchical-based Expression (HBE)-Multiple Constant Multiplication (MCM)-based multiplier architecture design for the 8-point DCT structure used in the video CODEC applications. The proposed work involves modified data path architecture and Floating Point Processing Element (FPPE) architecture. Our proposed design of the multipliers and DCT architecture requires minimum number of components when compared to the traditional DCT method. The HBE-MCM-based multiplier architecture includes shifters and adders. The number of Flip-Flops (FFs) and Look Up Tables (LUTs) used in the proposed architecture is reduced. The power consumption is reduced due to the reduction in the size of the components. This design is synthesized in VERILOG code language and implemented in the Field Programmable Gate Array (FPGA). The performance of the proposed architecture is evaluated by comparing it with traditional DCT architecture in terms of the Number of FFs, Number of LUTs, area, power, delay and speed.

Structure of an Embedded System Software Platform for Plate Recognition System Based on Applied Mechanics

2012 ◽  
Vol 460 ◽  
pp. 266-270
Author(s):  
Xing Wu Sun ◽  
Yu Chen ◽  
Ai Fei Wang
Keyword(s):  
Embedded System ◽  
Recognition System ◽  
Cmos Camera ◽  
Camera System ◽  
New Thought ◽  
Development Platform ◽  
Embedded Linux System ◽  
Acquisition Device ◽  
The Embedded System ◽  
And Control

According to the shortcomings of large volume and high cost about the plate recognition system, an embedded plate recognition system is developed based on the ARM11 processor at lower costs. Taking the embedded Linux system as the software development platform, the system uses graphical user interface to operate and control the machine. Using CMOS camera system as image acquisition device, the system adopts HSV algorithm to realize the image classification on the platform of the embedded plate recognition system. The experimental results show that the embedded system runs stably, can realize the plate classification by color, and has the advantages of small size, low power consumption, convenience for using and so on. The embedded system provides a new thought for plate recognition.

scholarly journals On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Y. Guillemenet ◽  
L. Torres ◽  
G. Sassatelli ◽  
N. Bruchon
Keyword(s):  
Power Consumption ◽  
Random Access ◽  
Switching Scheme ◽  
Fpga Design ◽  
Gate Arrays ◽  
Magnetic Switching ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Time Required ◽  
Magnetic Tunneling

This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design. The nonvolatility of the latter is achieved through the use of magnetic tunneling junctions (MTJs) in the MRAM cell. A thermally assisted switching scheme helps to reduce power consumption during write operation in comparison to the writing scheme in the FIMS-MTJ device. Moreover, the nonvolatility of such a design based on either an FIMS or a TAS writing scheme should reduce both power consumption and configuration time required at each power up of the circuit in comparison to classical SRAM-based FPGAs. A real-time reconfigurable (RTR) micro-FPGA using FIMS-MRAM or TAS-MRAM allows dynamic reconfiguration mechanisms, while featuring simple design architecture.

Design of GTAW Wire Feeder Control System Based on Nios II

2013 ◽  
Vol 397-400 ◽  
pp. 1909-1912 ◽  
Author(s):  
Fu Yang ◽  
Shu Zhang ◽  
Wen Ming Zhang
Keyword(s):  
Control System ◽  
Digital Control ◽  
Embedded Processor ◽  
Control Module ◽  
Nios Ii ◽  
Gas Tungsten Arc ◽  
Welding Arc ◽  
Current Parameter ◽  
Wire Feeding ◽  
Feeding Control

Based on Nios II embedded processor control module, a digital control system was designed for wire feeding control of gas tungsten arc welding(GTAW). In the control system FPGA wave module is used to control the movement of the DC servo motor, and the digital control of pulsed wire feeder for GTAW was achieved. One and the same control module with Nios II embedded processor is used to control the wire feeder and the welding power source. Thus, the current parameter of pulsed welding arc can be obtained and used directly for controlling the speed of wire feeding. At last, the experiment results are provided to verify the validity.

scholarly journals Low-Power Pedestrian Detection System on FPGA

Proceedings ◽  
2019 ◽  
Vol 31 (1) ◽  
pp. 35 ◽  
Author(s):  
Vinh Ngo ◽  
David Castells-Rufas ◽  
Arnau Casadevall ◽  
Marc Codina ◽  
Jordi Carrabina
Keyword(s):  
Low Power ◽  
Detection System ◽  
Low Cost ◽  
Pedestrian Detection ◽  
Support Vector ◽  
Embedded Processor ◽  
Car Industry ◽  
Field Programmable ◽  
On Chip ◽  
Histogram Of Gradients

Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

Exploiting Energy–Quality (E–Q) Tradeoffs: A Case Study on Color-to-Grayscale Converters with Approximate Design on FPGA

2020 ◽  
pp. 2150062
Author(s):  
Xiaokun Yang ◽  
Shi Sha
Keyword(s):  
Video Processing ◽  
Energy Savings ◽  
Experimental Result ◽  
Approximate Design ◽  
Diverse Range ◽  
Output Quality ◽  
Finite State ◽  
Field Programmable

Today, field programmable gate array (FPGA) is becoming widely used as computational accelerators in many application domains such as image/video processing, machine learning, and data mining. The inherent tolerance to the imprecise computation in such domains potentially provides an opportunity to trade quality of the results for higher energy efficiency. Therefore, this paper proposes a systematic methodology aiming to find the optimal energy saving corresponding to different quality bound, by approximating register-transfer level (RTL) designs on FPGA. As a case study, first, we investigate imprecise design on two submodules — adders and multipliers. By integrating the two combinational submodules with finite state machines (FSMs), several designs on a sequential circuit — color-to-grayscale converter — are further presented to offer a diverse range of energy consumption related to different quality constrains. Through this, we are able to set energy–quality (E–Q) parameters of our proposed methodology and configure the approximation knobs, capable of maximizing energy savings within different application-based quality margins. Experimental result demonstrates that leveraging E–Q leads to an average [Formula: see text]–[Formula: see text] savings in energy for modest loss in application output quality ([Formula: see text]), and [Formula: see text]–[Formula: see text] energy savings for impact on relaxed quality constraints (3–7.5%).

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