scholarly journals Efficient File Delivery for Coded Prefetching in Shared Cache Networks With Multiple Requests Per User

2019 ◽  
Vol 67 (4) ◽  
pp. 2849-2865
Author(s):  
Haisheng Xu ◽  
Chen Gong ◽  
Xiaodong Wang
Keyword(s):  
Shared Cache ◽  
Cache Networks

Fundamental Limits of Stochastic Shared-Cache Networks

2021 ◽  
pp. 1-1
Author(s):  
Adeel Malik ◽  
Berksan Serbetci ◽  
Emanuele Parrinello ◽  
Petros Elia
Keyword(s):  
Fundamental Limits ◽  
Shared Cache ◽  
Cache Networks

Performance of shared cache for parallel-pipelined computer systems

1983 ◽  
Vol 11 (3) ◽  
pp. 117-123 ◽  
Author(s):  
Phil C. C. Yeh ◽  
Janak H. Patel ◽  
Edward S. Davidson
Keyword(s):  
Computer Systems ◽  
Shared Cache ◽  
Parallel Pipelined

Exploring the design space for a shared-cache multiprocessor

1994 ◽  
Vol 22 (2) ◽  
pp. 166-175 ◽  
Author(s):  
B. A. Nayfeh ◽  
K. Olukotun
Keyword(s):  
Design Space ◽  
Shared Cache

Shared cache architectures for decision support systems

2002 ◽  
Vol 49 (1-4) ◽  
pp. 283-298 ◽  
Author(s):  
Michel Dubois ◽  
Jaeheon Jeong ◽  
Ashwini Nanda
Keyword(s):  
Decision Support ◽  
Decision Support Systems ◽  
Support Systems ◽  
Shared Cache

Static Analysis of Run-Time Inter-Core Interferences for Concurrent Programs in Shared Cache Multicore Architectures

2012 ◽  
Vol 198-199 ◽  
pp. 523-527
Author(s):  
Fang Yuan Chen ◽  
Dong Song Zhang ◽  
Zhi Ying Wang
Keyword(s):  
Multicore Processors ◽  
Mapping Method ◽  
Concurrent Programs ◽  
Multicore Architectures ◽  
Shared Resources ◽  
Worst Case ◽  
Shared Cache ◽  
Address Mapping ◽  
Novel Approach ◽  
Time Systems

Worst-Case Execution Time (WCET) is crucial in real-time systems and is very challenging in multicore processors due to the possible runtime inter-thread interferences caused by shared resources. This paper proposes a novel approach to analyze runtime inter-core interferences for consecutive or inconsecutive concurrent programs. Our approach can reasonably estimate runtime inter-core interferences in shared cache by introducing lifetime and instruction fetching timing relations analysis into address mapping method. Compared with the method based on lifetime alone, our proposed approach efficiently improves the tightness of WCET estimation.

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