Static Analysis of Run-Time Inter-Core Interferences for Concurrent Programs in Shared Cache Multicore Architectures

2012 ◽  
Vol 198-199 ◽  
pp. 523-527
Author(s):  
Fang Yuan Chen ◽  
Dong Song Zhang ◽  
Zhi Ying Wang
Keyword(s):  
Multicore Processors ◽  
Mapping Method ◽  
Concurrent Programs ◽  
Multicore Architectures ◽  
Shared Resources ◽  
Worst Case ◽  
Shared Cache ◽  
Address Mapping ◽  
Novel Approach ◽  
Time Systems

Worst-Case Execution Time (WCET) is crucial in real-time systems and is very challenging in multicore processors due to the possible runtime inter-thread interferences caused by shared resources. This paper proposes a novel approach to analyze runtime inter-core interferences for consecutive or inconsecutive concurrent programs. Our approach can reasonably estimate runtime inter-core interferences in shared cache by introducing lifetime and instruction fetching timing relations analysis into address mapping method. Compared with the method based on lifetime alone, our proposed approach efficiently improves the tightness of WCET estimation.

Novel prioritized LRU circuits for shared cache in computer systems

2020 ◽  
Vol 34 (23) ◽  
pp. 2050242
Author(s):  
Yao Wang ◽  
Lijun Sun ◽  
Haibo Wang ◽  
Lavanya Gopalakrishnan ◽  
Ronald Eaton
Keyword(s):  
Real Time ◽  
High Performance ◽  
Cmos Technology ◽  
Cache Replacement ◽  
Worst Case ◽  
Shared Cache ◽  
Cache Access ◽  
Worst Case Execution Time ◽  
Real Time Applications ◽  
Time Systems

Cache sharing technique is critical in multi-core and multi-threading systems. It potentially delays the execution of real-time applications and makes the prediction of the worst-case execution time (WCET) of real-time applications more challenging. Prioritized cache has been demonstrated as a promising approach to address this challenge. Instead of the conventional prioritized cache schemes realized at the architecture level by using cache controllers, this work presents two prioritized least recently used (LRU) cache replacement circuits that directly accomplish the prioritization inside the cache circuits, hence significantly reduces the cache access latency. The performance, hardware and power overheads due to the proposed prioritized LRU circuits are investigated based on a 65 nm CMOS technology. It shows that the proposed circuits have very low overhead compared to conventional cache circuits. The presented techniques will lead to more effective prioritized shared cache implementations and benefit the development of high-performance real-time systems.

scholarly journals Worst-Case Analysis of Digital Control Loops with Uncertain Input/Output Timing

10.29007/c4zl ◽  
2019 ◽  
Author(s):  
Maximilian Gaukler ◽  
Peter Ulbrich
Keyword(s):  
Control Systems ◽  
Digital Control ◽  
Worst Case Analysis ◽  
Real Time Systems ◽  
Input Output ◽  
Worst Case ◽  
Control Loops ◽  
Digital Control Systems ◽  
Uncertain Input ◽  
Time Systems

Benchmark Proposal: The implementation of digital control systems in complex multi- core or distributed real-time systems results in non-deterministic input/output timing. Such timing deviations typically lead to degraded performance or even instability, which in turn may jeopardize safety goals. We present the problem of proving worst-case guarantees for given input/output timing bounds as a benchmark for the verification of hybrid dynamical systems.

scholarly journals Dynamic approach to minimize overhead and response time in scheduling periodic real-time tasks

2021 ◽  
Vol 8 (4) ◽  
pp. 75-81
Author(s):  
Ahmed A. Alsheikhy ◽  
Keyword(s):  
Response Time ◽  
Real Time ◽  
Periodic Tasks ◽  
Dynamic Priority ◽  
New Novel ◽  
Context Switching ◽  
Novel Approach ◽  
Efficiency And Effectiveness ◽  
Time Systems ◽  
The Given

In real-time systems, a task or a set of tasks needs to be executed and completed successfully within a predefined time. Those systems require a scheduling technique or a set of scheduling methods to distribute the given task or the set of tasks among different processors or on a processor. In this paper, a new novel scheduling approach to minimize the overhead from context switching between several periodic tasks is presented. This method speeds up a required response time while ensuring that all tasks meet their deadline times and there is no deadline miss occurred. It is a dynamic-priority technique that works either on a uniprocessor or several processors. In particular, it is proposed to be applied on multiprocessor environments since many applications run on several processors. Various examples are presented within this paper to demonstrate its optimality and efficiency. In addition, several comparison experiments with an earlier version of this approach were performed to demonstrate its efficiency and effectiveness too. Those experiments showed that this novel approach sped up the execution time from 15% to nearly around 46%. In addition, it proved that it reduced the number of a context switch between tasks from 12% to around 50% as shown from simulation tests. Furthermore, this approach delivered all tasks/jobs successfully and ensured there was no deadline miss happened.

Use of Measurements in Worst-Case Execution Time Estimation for Real-Time Systems

2021 ◽  
Author(s):  
Jessica Junia Santillo Costa ◽  
Romulo Silva de Oliveira ◽  
Luis Fernando Arcaro
Keyword(s):  
Real Time ◽  
Execution Time ◽  
Time Estimation ◽  
Real Time Systems ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Time Systems

Memory-Aware Scheduling Parallel Real-Time Tasks for Multicore Systems

2021 ◽  
Vol 31 (04) ◽  
pp. 613-634
Author(s):  
Zhenyang Lei ◽  
Xiangdong Lei ◽  
Jun Long
Keyword(s):  
Real Time ◽  
Data Access ◽  
Main Memory ◽  
Second Phase ◽  
Shared Resources ◽  
Access Memory ◽  
Worst Case ◽  
Scheduling Policy ◽  
The Core ◽  
Level Scheduling

Shared resources on the multicore chip, such as main memory, are increasingly becoming a point of contention. Traditional real-time task scheduling policies focus on solely on the CPU, and do not take in account memory access and cache effects. In this paper, we propose parallel real-time tasks scheduling (PRTTS) policy on multicore platforms. Each set of tasks is represented as a directed acyclic graph (DAG). The priorities of tasks are assigned according to task periods Rate Monotonic (RM). Each task is composed of three phases. The first phase is read memory stage, the second phase is execution phase and the third phase is write memory phase. The tasks use locks and critical sections to protect data access. The global scheduler maintains the task pool in which tasks are ready to be executed which can run on any core. PRTTS scheduling policy consists of two levels: the first level scheduling schedules ready real-time tasks in the task pool to cores, and the second level scheduling schedules real-time tasks on cores. Tasks can preempt the core on running tasks of low priority. The priorities of tasks which want to access memory are dynamically increased above all tasks that do not access memory. When the data accessed by a task is in the cache, the priority of the task is raised to the highest priority, and the task is scheduled immediately to preempt the core on running the task not accessing memory. After accessing memory, the priority of these tasks is restored to the original priority and these tasks are pended, the preempted task continues to run on the core. This paper analyzes the schedulability of PRTTS scheduling policy. We derive an upper-bound on the worst-case response-time for parallel real-time tasks. A series of extensive simulation experiments have been performed to evaluate the performance of proposed PRTTS scheduling policy. The results of simulation experiment show that PRTTS scheduling policy offers better performance in terms of core utilization and schedulability rate of tasks.

A Novel Approach to Realistic Worst-case Simulations of CMOS Circuits

ESSDERC ’89 ◽  
1989 ◽  
pp. 310-313 ◽  
Author(s):  
M. J. B. Bolt ◽  
J. Engel ◽  
M. Rocchi ◽  
A. van Steenwijk
Keyword(s):  
Cmos Circuits ◽  
Worst Case ◽  
Novel Approach
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