An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

2015 ◽  
pp. 1-10 ◽  
Author(s):  
Indranil Hatai ◽  
Indrajit Chakrabarti ◽  
Swapna Banerjee
Keyword(s):  
Fir Filter ◽  
Filter Synthesis ◽  
Elimination Algorithm ◽  
Constant Multiplier

scholarly journals Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 6138-6141
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Propagation Delay ◽  
Fir Filter ◽  
Filter Synthesis ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Effective Performance

32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

Efficient FIR Filter Synthesis Using Sigmoidal Function

2019 ◽  
Author(s):  
Peter Stoyanov Apostolov ◽  
Alexey Kostadinov Stefanov ◽  
Mariya Simeonova Bagasheva
Keyword(s):  
Fir Filter ◽  
Sigmoidal Function ◽  
Filter Synthesis
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