Performance evaluation of wireless local area network with congested fading channels

The IEEE 802.11ay wireless communication standard consents gadgets to link in the spectrum of millimeter wave (mm-Wave) 60 Giga Hertz band through 100 Gbps bandwidth. The development of promising high bandwidth in communication networks is a must as QoS, throughput and error rates of bandwidth-intensive applications like merged reality (MR), artificial intelligence (AI) related apps or wireless communication boggling exceed the extent of the chronic 802.11 standard established in 2012. Thus, the IEEE 802.11ay task group committee has newly amended recent physical (PHY) and medium access control (MAC) blueprints to guarantee a technical achievement especially in link delay on multipath fading channels (MPFC). However, due to the congestion of super bandwidth intensive apps such as IoT and big data, we propose to diversify a propagation delay to practical extension. This article then focuses on a real-world situation and how the IEEE 802.11ay design is affected by the performance of mm-Wave propagation. In specific, we randomize the unstable MPFC link capacity by taking the divergence of congested network parameters into account. The efficiency of congested MPFC-based wireless network is simulated and confirmed by advancements described in the standard.

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

An Efficient Metaheuristic-Based Clustering with Routing Protocol for Underwater Wireless Sensor Networks

In recent years, the underwater wireless sensor network (UWSN) has received a significant interest among research communities for several applications, such as disaster management, water quality prediction, environmental observance, underwater navigation, etc. The UWSN comprises a massive number of sensors placed in rivers and oceans for observing the underwater environment. However, the underwater sensors are restricted to energy and it is tedious to recharge/replace batteries, resulting in energy efficiency being a major challenge. Clustering and multi-hop routing protocols are considered energy-efficient solutions for UWSN. However, the cluster-based routing protocols for traditional wireless networks could not be feasible for UWSN owing to the underwater current, low bandwidth, high water pressure, propagation delay, and error probability. To resolve these issues and achieve energy efficiency in UWSN, this study focuses on designing the metaheuristics-based clustering with a routing protocol for UWSN, named MCR-UWSN. The goal of the MCR-UWSN technique is to elect an efficient set of cluster heads (CHs) and route to destination. The MCR-UWSN technique involves the designing of cultural emperor penguin optimizer-based clustering (CEPOC) techniques to construct clusters. Besides, the multi-hop routing technique, alongside the grasshopper optimization (MHR-GOA) technique, is derived using multiple input parameters. The performance of the MCR-UWSN technique was validated, and the results are inspected in terms of different measures. The experimental results highlighted an enhanced performance of the MCR-UWSN technique over the recent state-of-art techniques.

Assessment of Effective Network Connectivity among MEG None Contaminated Epileptic Transitory Events

Characterizing epileptogenic zones EZ (sources responsible of excessive discharges) would assist a neurologist during epilepsy diagnosis. Locating efficiently these abnormal sources among magnetoencephalography (MEG) biomarker is obtained by several inverse problem techniques. These techniques present different assumptions and particular epileptic network connectivity. Here, we proposed to evaluate performances of distributed inverse problem in defining EZ. First, we applied an advanced technique based on Singular Value Decomposition (SVD) to recover only pure transitory activities (interictal epileptiform discharges). We evaluated our technique’s robustness in separation between transitory and ripples versus frequency range, transitory shapes, and signal to noise ratio on simulated data (depicting both epileptic biomarkers and respecting time series and spectral properties of realistic data). We validated our technique on MEG signal using detector precision on 5 patients. Then, we applied four methods of inverse problem to define cortical areas and neural generators of excessive discharges. We computed network connectivity of each technique. Then, we confronted obtained noninvasive networks to intracerebral EEG transitory network connectivity using nodes in common, connection strength, distance metrics between concordant nodes of MEG and IEEG, and average propagation delay. Coherent Maximum Entropy on the Mean (cMEM) proved a high matching between MEG network connectivity and IEEG based on distance between active sources, followed by Exact low-resolution brain electromagnetic tomography (eLORETA), Dynamical Statistical Parametric Mapping (dSPM), and Minimum norm estimation (MNE). Clinical performance was interesting for entire methods providing in an average of 73.5% of active sources detected in depth and seen in MEG, and vice versa, about 77.15% of active sources were detected from MEG and seen in IEEG. Investigated problem techniques succeed at least in finding one part of seizure onset zone. dSPM and eLORETA depict the highest connection strength among all techniques. Propagation delay varies in this range [18, 25]ms, knowing that eLORETA ensures the lowest propagation delay (18 ms) and the closet one to IEEG propagation delay.

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10, 100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

Cascoded GaN half-bridge with 17-MHz wide-band galvanically isolated current sensor

A cascoded GaN half-bridge with wide-band galvanically isolated current sensor is proposed. A 650-V depletion-mode GaN FET is switched by a low-propagation-delay gate driver in active-mode. The standby and active modes are switched by a 25-V N-ch LDMOS. The current sensor uses the LDMOS as a shunt resistor, gm-cell-based sense amplifier and mixer based isolation amplifier for wider bandwidth. PVT variations of on-resistance of the current-detecting MOSFET are compensated using a reference MOSFET. A digital calibration loop across the isolation is formed to keep the current sensor gain constant within ±1.5% across the whole temperature range. The wide-band current sensor can measure power device switching current. In this study, a cascoded GaN half-bridge switching and inductor current sensing using low-side and high-side device current are demonstrated. The proposed techniques show the possibility of implementing a GaN half-bridge module with isolated current sensor in a package.

Design of JL-CFET(junctionless complementary field effect transistor)-based inverter for low power applications

Junctionless complementary field effect transistor (JL-CFET) is an emerging device that needs a small layout area and low fabrication cost. However, in order for the JL-CFET to be adopted for low power applications, two main constraints need to be overcome: (1) a high work function of metal gate and (2) a low drain current. In this work, an optimal device design is proposed to overcome those problems, by analyzing various performance metrics, such as on-state drive current, subthreshold swing, drain induced barrier lowering, propagation delay time, and ring oscillator’s oscillation frequency, which are extracted from various structures of JL-CFET. In addition, the negative capacitance effect in JL-CFET is examined to address the limit from device structures.

Compensation for Delays and Losses of Packages in Dynamic Online Games

A couple of decades ago, data rates on the network were measured in kilobytes per second, and even then, online game developers had some problems with the packet loss and transmission delays. Now the transfer rate is hundreds of times higher, and the problem of delay compensation is even more relevant.For many dynamic online games, a transmission delay of as little as 20 ms can be quite noticeable, negatively affecting the gameplay and emotions of the game, which can repel players.The problem is exacerbated by the fact that along with the need to compensate for the time of delivery of packets, on the client side there are other non-network factors that are beyond the control of developers, which make the total delay 5-10 ms longer. Because of this, the desire to get rid of network delays as much and as well as possible becomes a necessity, and developers are forced to look for optimal ways to solve this problem.The problem statement is as follows: to review the causes of delays in online games and possible solu- tions, as well as the advantages and disadvantages of certain approaches. The problem is considered at the 4 levels of the TCP / IP network model, as well as at the application level. The approaches are given for the most commonly used protocols for each layer, but basic ideas can be easily transferred to other implementations.The main causes of delays under consideration: propagation delay, router queue delay, transmission delay, and processing delays.This article shows the impact of network delays on the online games and the ways to compensate for them, along with the theory of data transmission protocols in the network and the ways to solve the problems that arise in the development of algorithms.Recommendations for solving the compensation problem can be taken into account when designing and launching online shooters, strategies, etc. Thanks to the given receptions it is possible to minimize the general delay on the transfer of packets in a network, thanks to which the game on the client looks as if the player plays in the Single Player mode.