Design and Implementation of Carbon Nano-tube based Full Adder at 32nm Technology for High Speed and Power Efficient Arithmetic Applications

Due to physical, material, technological, power-thermal and economical difficulties, scaling of CMOS transistors will stop very soon. Due to efficiency of power and speed compared to CMOS transistors, Carbon Nano-tube transistors are best suitable element to design logic circuits. So, CNTFETS have been utilized in designing of proposed full adder (FA) and 4-bit ripple carry adder (RCA) in this paper. Proposed FA and RCA have been compared to rival designs on bases of power, speed and power-delay-product (PDP). FA and RCA circuits have been analysed with the variation of temperature from 0°C to 100°C while the variation of supply voltages is from 0.7V to 1.3V. For all temperatures and all supply voltages, proposed FA and proposed RCA have the least power consumption, shortest delay and lowest PDP. SPICE has been utilized for simulating FAs and RCAs in 32 nm process node. Even though the fabrication is complicated than CMOS counterparts but simulation results confirm usefulness of proposed FA and RCA for high speed and power efficient arithmetic applications.

Low power and area efficient design of fir filter using enhanced clock gating technique

The main aim of this approach is to improve the design model of filters for optimal circuit design. The objective of this proposed method is to improve the performance of VLSI circuit like area, power, and delay. In recent days, the filters are most applicable designs in DSP, medical diagnosis and arithmetic computations. In Digital Signal Processing and communication applications, the FIR filter plays an important role. The Finite Impulse Response is designed with number of adders, multipliers, subtraction units, transfer functions and delay elements. The VLSI circuits are applied in various applications, but the number adders and multipliers occupy the design space since it increases the area and delay factors. The main aim is to reduce the number of adders and multiplier by various computational algorithms. The existing research work uses carry save accumulator with ripple carry adder and binary multiplier. In proposed method, the enhanced Vedic multiplication logic and improved carry lookahead adder logic improves the result. In Vedic multiplication algorithm, the number of adder logic is minimized by adding speculative Brent-kung adder logic in it. The fastest adder in VLSI circuit is CLA (Carry look ahead adder logic), which is improved by utilizing the result of reduced power consumption and delay. In this proposed research work, the power optimization is done by using enhanced clock gating technique. Here, area, power, and delay factors are measured and it is compared with conventional FIR filter design. The proposed method improves the result in the way of area, power, and delay. The whole FIR filter structure is designed and power optimized by connecting with an enhanced clock gating technique. This proposed design and simulate by using Xilinx ISE 14.5 and it is synthesize by ModelSim.

Performance of Adder Architectures on Encrypted Integers

The fully Homomorphic encryption scheme is corner stone of privacy in an increasingly connected world. It allows to perform all kinds of computations on encrypted data. Although, time of computations is bottleneck of numerous applications of real life. In this paper, a brief description is made on the homomorphic encryption scheme TFHE of Illaria Chillota and the others. TFHE, implemented in c language in a library, improves the bootstrapping execution time of the FHEW scheme to 13 milliseconds. TFHE performs homomorphic processing on a multitude of logic gates. This variety made it possible to construct, implement five adder architectures and compare them in terms of the execution time of the bootstrapping per logic gate. In a singleprocessor computing environment, the Carry Look-ahead Adder completed a two-integer addition in 90 seconds, whereas the Ripple carry Adder did the same processing in 109 seconds. An improvement in processing time of 15% is observed. And, the same ratio of about 15% was obtained on four integers, respectively for 279 seconds for the first adder and 320 seconds for Wallace's dedicated adder. While in the dual-processor environment, a 50% improvement was seen on all adders in the same processing on integers. The Carry Look-ahead Adder saw his handling improved by the sum of two numbers from 90 seconds to 46 seconds and four numbers from 279 seconds to 139 seconds, respectively.

A High-Speed Parallel Architecture for Ripple Carry Adder with Fault Detection and Localization

Ripple-carry adder (RCA) is among the most common type of adder. However, it is not preferred in many applications because of its high latency. In this paper, two architectures of high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, with reduced overhead as compared with carry look-ahead adder (CLA). In the proposed approach, RCA is divided into blocks, where the initial carry input for each block will be generated by a carry look-ahead logic unit. The delay is reduced by 43.81% as compared with the conventional 64-bit RCA design. The delay is further reduced by replacing the last blocks with a single RCA-based CSeA design and becomes equal to CLA if the last three blocks are replaced with CSeA. The proposed 64-bit design of PRCA and PRCA-CSeA requires 20.31% and 22.50% area overhead as compared with the conventional RCA design. Whereas, the delay-power-area product of our proposed designs is 24.66%, and 30.94% more efficient than conventional RCA designs. With self-checking, the proposed architecture of PRCA and PRCA-CSeA with multiple-fault detection requires 42.36% and 44.35% area overhead as compared with a 64-bit self-checking RCA design.

COMPARISON AND ANALYSIS OF PERFORMANCE PARAMETERS OF BASIC ADDERS WITH SPARSE ADDER

Adders play a vital role in the design of a digital system using VLSI (Very Large Scale Integration) technique. Adders are the basic building block of ALU (Arithmetic Logic Unit) which is an important component of a processor. In this paper we are comparing and analyzing the performance parameters of basic adders like Ripple Carry Adder, Carry Select Adder, Carry Look Ahead Adder, Parallel Prefix Adder along with sparse adder. The above mentioned adders are implemented using 90nm technology in Xilinx ISE 14.7 Suite.

A REVIEW OF LOW VOLTAGE AND LOW POWER CMOS ADDERS USING VLSI DESIGN IN VERILOG/VHDL

The dominant portion of power dissipation in CMOS adder circuits, due to logic transitions, varies as the square of the supply, significant savings in power dissipation may be exacted by operating with reduced supply voltage. If the supply voltage is reduced while threshold voltage stays same, the noise margins will reduce. Addition is a crucial process because it usually involve carry ripple steps which must propagate a carry signal from each bit to it’s higher bit position. This results in a substantial circuit delay. The adder which lies in the crucial delay path will effectively determine the system overall speed. To improve noise margins, the threshold voltages must also be made smaller. However subthreshold leakage current increases exponentially when threshold voltage is reduced. The higher static dissipation may then offset the reduction in transitions portion of the dissipation. Hence the devices needed to have threshold voltages that maximizes the net reduction in the dissipation. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. Due to the potential versatility of adders in this contemporary research field, the existing adders and adder designs currently intended for future low voltage and low power environments. This can be achieved by the CMOS adders namely Parallel Adder, Ripple Carry Adder(RCA), Carry Look Ahead Adder(CLA), Carry Select Adder(CSL), Carry Save Adder(CSA), Carry Skip Adder(CSK), Conditional Sum Adder(COS).

A new design for 4-bit RCA using Quantum Cellular Automata Technology

Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.