A Fully Serial-In Parallel-Out Digit-Level Finite Field Multiplier in $\mathbb {F}_{2^{m}}$ Using Redundant Representation

A High-Speed Word Level Finite Field Multiplier in ${\BBF}_{2^m}$ Using Redundant Representation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2003005 ◽

2009 ◽

Vol 17 (10) ◽

pp. 1546-1550 ◽

Cited By ~ 6

Author(s):

A.H. Namin ◽

Huapeng Wu ◽

M. Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Word Level ◽

Finite Field Multiplier ◽

An Efficient Finite Field Multiplier Using Redundant Representation

ACM Transactions on Embedded Computing Systems ◽

10.1145/2220336.2220343 ◽

2012 ◽

Vol 11 (2) ◽

pp. 1-14 ◽

Cited By ~ 4

Author(s):

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Finite Field Multiplier ◽

Finite field multiplier using redundant representation

IEEE Transactions on Computers ◽

10.1109/tc.2002.1047755 ◽

2002 ◽

Vol 51 (11) ◽

pp. 1306-1316 ◽

Cited By ~ 51

Author(s):

Huapeng Wu ◽

M.A. Hasan ◽

I.F. Blake ◽

Shuhong Gao

Keyword(s):

Finite Field ◽

Finite Field Multiplier ◽

A New Finite-Field Multiplier Using Redundant Representation

IEEE Transactions on Computers ◽

10.1109/tc.2007.70834 ◽

2008 ◽

Vol 57 (5) ◽

pp. 716-720 ◽

Cited By ~ 11

Author(s):

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Finite Field Multiplier ◽

High speed VLSI implementation of a finite field multiplier using redundant representation

10.1109/ecctd.2009.5274961 ◽

2009 ◽

Author(s):

Ashkan Hosseinzadeh Namin ◽

Karl Leboeuf ◽

Roberto Muscedere ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Vlsi Implementation ◽

Finite Field Multiplier ◽

A high speed word level finite field multiplier using reordered normal basis

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4542158 ◽

2008 ◽

Cited By ~ 5

Author(s):

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Normal Basis ◽

Word Level ◽

Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2018.2851958 ◽

2018 ◽

Vol 26 (11) ◽

pp. 2542-2552

Author(s):

Parham Hosseinzadeh Namin ◽

Crystal Roma ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Vlsi Implementation ◽

Domino Logic ◽

Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula

2011 Fifth International Conference on Genetic and Evolutionary Computing ◽

10.1109/icgec.2011.62 ◽

2011 ◽

Cited By ~ 1

Author(s):

Chiou-Yng Lee ◽

Pramod Kumar Meher

Keyword(s):

Finite Field ◽

Toeplitz Matrix ◽

Product Formula ◽

Inner Product ◽

Finite Field Multiplier ◽

Matrix Vector

Low power design of a word-level finite field multiplier using Reordered Normal Basis

2015 49th Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2015.7421165 ◽

2015 ◽

Author(s):

Parham Hosseinzadeh Namin ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Low Power ◽

Low Power Design ◽

Normal Basis ◽

Word Level ◽

Efficient VLSI implementation of a finite field multiplier using reordered normal basis

2010 53rd IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2010.5548774 ◽

2010 ◽

Cited By ~ 1

Author(s):

Karl Leboeuf ◽

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Vlsi Implementation ◽