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Compact FPGA implementation of 32-bits AES algorithm using Block RAM
TENCON 2007 - 2007 IEEE Region 10 Conference
◽
10.1109/tencon.2007.4429126
◽
2007
◽
Cited By ~ 4
Author(s):
Chi-Wu Huang
◽
Chi-Jeng Chang
◽
Mao-Yuan Lin
◽
Hung-Yun Tai
Keyword(s):
Fpga Implementation
◽
Aes Algorithm
Download Full-text
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Cited By
References
FPGA Implementation of Parallel Transformative Approach in AES Algorithm
Information and Communication Technology for Competitive Strategies - Lecture Notes in Networks and Systems
◽
10.1007/978-981-13-0586-3_34
◽
2018
◽
pp. 333-340
◽
Cited By ~ 1
Author(s):
Padma Prasada
◽
Sathisha
◽
Ajay Prinston Pinto
◽
H. D. Ranjith
Keyword(s):
Fpga Implementation
◽
Aes Algorithm
◽
Transformative Approach
Download Full-text
FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP
Microprocessors and Microsystems
◽
10.1016/j.micpro.2019.102972
◽
2020
◽
Vol 73
◽
pp. 102972
Author(s):
S. Madhavapandian
◽
P. MaruthuPandi
Keyword(s):
Fpga Implementation
◽
Aes Algorithm
◽
Replacement Technique
◽
Security Application
Download Full-text
AES Algorithm Optimization and FPGA Implementation
IOP Conference Series Earth and Environmental Science
◽
10.1088/1755-1315/267/4/042070
◽
2019
◽
Vol 267
◽
pp. 042070
Author(s):
Yufeng Liu
◽
Xiangyang Xu
◽
Hao Su
Keyword(s):
Fpga Implementation
◽
Algorithm Optimization
◽
Aes Algorithm
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FPGA implementation of AES algorithm using Composite Field Arithmetic
2012 International Conference on Devices, Circuits and Systems (ICDCS)
◽
10.1109/icdcsyst.2012.6188783
◽
2012
◽
Cited By ~ 5
Author(s):
N. Anitha Christy
◽
P. Karthigaikumar
Keyword(s):
Fpga Implementation
◽
Aes Algorithm
◽
Composite Field
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An Area-Throughput Efficient FPGA Implementation of the Block Cipher AES Algorithm
2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies
◽
10.1109/act.2009.88
◽
2009
◽
Cited By ~ 10
Author(s):
Banraplang Jyrwa
◽
Roy Paily
Keyword(s):
Block Cipher
◽
Fpga Implementation
◽
Aes Algorithm
Download Full-text
FPGA implementation of AES algorithm for high throughput using folded parallel architecture
Security and Communication Networks
◽
10.1002/sec.651
◽
2012
◽
Vol 7
(11)
◽
pp. 2225-2236
◽
Cited By ~ 20
Author(s):
K. Rahimunnisa
◽
P. Karthigaikumar
◽
Soumiya Rasheed
◽
J. Jayakumar
◽
S. SureshKumar
Keyword(s):
High Throughput
◽
Parallel Architecture
◽
Fpga Implementation
◽
Aes Algorithm
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Low area memory-free FPGA implementation of the AES algorithm
22nd International Conference on Field Programmable Logic and Applications (FPL)
◽
10.1109/fpl.2012.6339250
◽
2012
◽
Cited By ~ 23
Author(s):
Junfeng Chu
◽
Mohammed Benaissa
Keyword(s):
Fpga Implementation
◽
Low Area
◽
Aes Algorithm
Download Full-text
FPGA Implementation of High Speed VLSI Architectures for AES Algorithm
2012 Fifth International Conference on Emerging Trends in Engineering and Technology
◽
10.1109/icetet.2012.53
◽
2012
◽
Cited By ~ 10
Author(s):
R.V. Kshirsagar
◽
M.V. Vyawahare
Keyword(s):
High Speed
◽
Fpga Implementation
◽
Vlsi Architectures
◽
Aes Algorithm
Download Full-text
An Efficient FPGA Implementation of AES Algorithm
International Journal of Engineering Research and
◽
10.17577/ijertv5is100124
◽
2016
◽
Vol V5
(10)
◽
Author(s):
Avantika Patil
◽
Prof. R. A. Pagare
◽
Keyword(s):
Fpga Implementation
◽
Aes Algorithm
Download Full-text
Real-time efficient FPGA implementation of aes algorithm
2013 IEEE International SOC Conference
◽
10.1109/socc.2013.6749688
◽
2013
◽
Cited By ~ 10
Author(s):
Mazen El Maraghy
◽
Salma Hesham
◽
Mohamed A. Abd El Ghany
Keyword(s):
Real Time
◽
Fpga Implementation
◽
Aes Algorithm
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