A 20MHz On-Chip All-NMOS 3-Level DC-DC Converter with Interception Coupling Dead-Time Control and 3-Switch Bootstrap Gate Driver

Author(s):  
Bumkil Lee ◽  
D. Brian Ma
Keyword(s):  
IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Jun Tang ◽  
Tian Guo ◽  
Jung Sik Kim ◽  
Jeongjin Roh

2012 ◽  
Vol 562-564 ◽  
pp. 1531-1536
Author(s):  
Ming Xing Zhu ◽  
Jing Bo Shi

In the inverter control system, two-phase modulated space vector pulse width modulation (SVPWM) algorithm has the advantages of minimum switch loss and higher utilization of direct current (DC) bus voltage. Non-dead-time control strategy can eliminate the problems of the dead time effects. But the traditional non-dead-time control strategy heavily depends on the current zero-crossing detection, which may cause the output voltage distortion or even a short circuit. Based on the analysis of the reason for the distortion, a new optimized non-dead-time control method is proposed. Two methods for the detection of the overlapping area are enumerated. The conclusions are confirmed by the simulation results with MATLAB/ SIMULINK.


2019 ◽  
Vol 47 (1-2) ◽  
pp. 77-89
Author(s):  
Ujjaval J. Patel ◽  
Nilesh G. Chothani ◽  
Praghnesh J. Bhatt ◽  
Dhaval N. Tailor

Author(s):  
Roberto di Lorenzo ◽  
Osvaldo Gasparri ◽  
Albino Pidutti ◽  
Paolo del Croce ◽  
Andrea Baschirotto

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