Cascoded GaN half-bridge with 17-MHz wide-band galvanically isolated current sensor

A cascoded GaN half-bridge with wide-band galvanically isolated current sensor is proposed. A 650-V depletion-mode GaN FET is switched by a low-propagation-delay gate driver in active-mode. The standby and active modes are switched by a 25-V N-ch LDMOS. The current sensor uses the LDMOS as a shunt resistor, gm-cell-based sense amplifier and mixer based isolation amplifier for wider bandwidth. PVT variations of on-resistance of the current-detecting MOSFET are compensated using a reference MOSFET. A digital calibration loop across the isolation is formed to keep the current sensor gain constant within ±1.5% across the whole temperature range. The wide-band current sensor can measure power device switching current. In this study, a cascoded GaN half-bridge switching and inductor current sensing using low-side and high-side device current are demonstrated. The proposed techniques show the possibility of implementing a GaN half-bridge module with isolated current sensor in a package.

Gate Current in p-GaN Gate HEMTs as a Channel Temperature Sensitive Parameter: A Comparative Study between Schottky- and Ohmic-Gate GaN HEMTs

In this work, a comparison between the gate-driving requirements of p-GaN HEMTs with gate contact of Schottky and Ohmic type is presented. Furthermore, the presence of a gate current of different magnitude is experimentally verified for both types of devices. Successively, the possibility of using the gate current as a temperature-sensitive parameter and its monitoring during real circuit operation is proposed. The viability of monitoring the gate current without introducing additional complexity in the gate driver is examined through experimental measurements on commercially available p-GaN HEMTs.

VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.