Optimal Three-Dimensional Placement of Heat Generating Electronic Components

1997 ◽  
Vol 119 (2) ◽  
pp. 106-113 ◽  
Author(s):  
M. I. Campbell ◽  
C. H. Amon ◽  
J. Cagan
Keyword(s):  
Simulated Annealing ◽  
Simulated Annealing Algorithm ◽  
Three Dimensional ◽  
Heat Transfer Analysis ◽  
Placement Test ◽  
Test Cases ◽  
Electronic Components ◽  
Component Layout ◽  
Temperature Ranges ◽  
Annealing Algorithm

This work introduces an algorithm that uses simulated annealing to perform electronic component layout while incorporating constraints related to thermal performance. A hierarchical heat transfer analysis is developed which is used in conjunction with the simulated annealing algorithm to produce final layout configurations that are densely packed and operate within specified temperature ranges. Examples of three-dimensional component placement test cases are presented including an application to embedded wearable computers.

Three Dimensional Offline Packing Optimization Problem Based on Genetic Simulated Annealing Algorithm

2015 ◽  
Vol 744-746 ◽  
pp. 1919-1923
Author(s):  
Zhan Zhong Wang ◽  
Jing Fu ◽  
Lan Fang Liu ◽  
Rui Rui Liu
Keyword(s):  
Genetic Algorithm ◽  
Simulated Annealing ◽  
Optimization Problem ◽  
Simulated Annealing Algorithm ◽  
Three Dimensional ◽  
Packing Problem ◽  
Genetic Simulated Annealing Algorithm ◽  
Annealing Algorithm ◽  
Final Optimization ◽  
Packing Optimization

In this paper, we try to solve 3D offline packing optimization problem by combining two methods-genetic algorithm’ global performance and simulated annealing algorithm’ local performance. Given Heuristic rules in loading conditions, we use the optimal preservation strategy and the roulette wheel method to choose selection operator, integrating simulated annealing algorithm into genetic algorithm , and achieving code programming and algorithms by Matlab.This paper carries out an actual loading in a vehicle company in Changchun City, then makes a contrast between the final optimization results and each suppliers’ current packing data.The experimental results show that the algorithm has a certain validity and practicability in multiple container packing problem.

Comprehensive Improved Simulated Annealing Optimization for Floorplanning of Heterogeneous 3D Networks-on-Chip

2015 ◽  
Vol 15 (03n04) ◽  
pp. 1540006
Author(s):  
DAKUN ZHANG ◽  
GUOZHI SONG ◽  
KUNLIANG LIU ◽  
YONG MA ◽  
CHENGLONG ZHAO ◽  
...  
Keyword(s):  
Simulated Annealing ◽  
Optimization Algorithm ◽  
Simulated Annealing Algorithm ◽  
Three Dimensional ◽  
Network On Chip ◽  
Networks On Chip ◽  
3D Network ◽  
Annealing Algorithm ◽  
On Chip ◽  
3D Networks

With the rapid development of integrated circuit manufacturing processes, poor system scalability has become a prominent problem for System on Chip (SoC).To solve the bottleneck problems such as global synchronization, network on chip Networks on Chip (NoC) has emerged as a new design to tackle the increasing communication demand among elements on chips. With the development of networks-on-chip, the research has expanded from two-dimensional to three-dimensional design, and 3D networks-on-chip is a combination of 3D integration technology and 2D networks-on-chips with the advantages of both to meet the development trend of diversified chip functions. This paper presents an improved floorplanning optimization algorithm based on simulated annealing algorithm (Comprehensive Improved Simulated Annealing, hereinafter referred to as CISA algorithm) to replace the original floorplanning optimization algorithm based on simulated annealing algorithm (Simulated Annealing, hereinafter referred to as SA algorithm) to make it more applicable to the three-dimensional network-on- chip simulation. This paper describes the CISA algorithm improvement ideas and uses it on an existing 3D network-on-chip simulator with a set of classical simulation tests. The results show that the proposed CISA algorithm is better than the original SA algorithm and it is more suitable for simulations of three-dimensional networks-on-chip, especially when dealing with large scale 3D NoC.

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