scholarly journals Design of a stateless low-latency router architecture for green software-defined networking

2015 ◽  
Author(s):  
Silvia Saldaña Cercós ◽  
Ramon M. Ramos ◽  
Ana C. Ewald Eller ◽  
Magnos Martinello ◽  
Moisés R. N. Ribeiro ◽  
...  
Keyword(s):  
Software Defined Networking ◽  
Low Latency ◽  
Router Architecture ◽  
Green Software

Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip

2014 ◽  
Vol 35 (2) ◽  
pp. 341-346
Author(s):  
Xiao-fu Zheng ◽  
Hua-xi Gu ◽  
Yin-tang Yang ◽  
Zhong-fan Huang
Keyword(s):  
Network On Chip ◽  
Low Latency ◽  
Router Architecture ◽  
On Chip

scholarly journals Prediction router: Yet another low latency on-chip router architecture

2009 ◽  
Author(s):  
Hiroki Matsutani ◽  
Michihiro Koibuchi ◽  
Hideharu Amano ◽  
Tsutomu Yoshinaga
Keyword(s):  
Low Latency ◽  
Router Architecture ◽  
On Chip

A practical low-latency router architecture with wing channel for on-chip network

2011 ◽  
Vol 35 (2) ◽  
pp. 98-109 ◽  
Author(s):  
Mingche Lai ◽  
Lei Gao ◽  
Sheng Ma ◽  
Xiao Nong ◽  
Zhiying Wang
Keyword(s):  
Low Latency ◽  
Router Architecture ◽  
On Chip

scholarly journals Sleeping mode of multi-controller in green software-defined networking

2016 ◽  
Vol 2016 (1) ◽  
Author(s):  
Chao Qiu ◽  
Chenglin Zhao ◽  
Fangmin Xu ◽  
Tianpu Yang
Keyword(s):  
Software Defined Networking ◽  
Green Software

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

2011 ◽  
Vol 60 (6) ◽  
pp. 783-799 ◽  
Author(s):  
Hiroki Matsutani ◽  
Michihiro Koibuchi ◽  
Hideharu Amano ◽  
Tsutomu Yoshinaga
Keyword(s):  
Low Latency ◽  
Router Architecture ◽  
On Chip
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