Low-density parity-check codes based on steiner systems and permutation matrices

2013 ◽  
Vol 49 (4) ◽  
pp. 333-347 ◽  
Author(s):  
F. I. Ivanov ◽  
V. V. Zyablov
2005 ◽  
Vol 41 (1) ◽  
pp. 33-44 ◽  
Author(s):  
A. Sridharan ◽  
M. Lentmaier ◽  
D. V. Truhachev ◽  
D. J. Costello ◽  
K. Sh. Zigangirov

Author(s):  
Mohammed Amine Tehami ◽  
Ali Djebbari

In this paper, a new technique for constructing low density parity check codes based on the Hankel matrix and circulant permutation matrices is proposed. The new codes are exempt of any cycle of length 4. To ensure that parity check bits can be recursively calculated with linear computational complexity, a dual-diagonal structure is applied to the parity check matrices of those codes. The proposed codes provide a very low encoding complexity and reduce the stored memory of the matrix H in which this matrix can be easily implemented comparing to others codes used in channel coding. The new LDPC codes are compared, by simulation, with uncoded bi-phase shift keying (BPSK). The result shows that the proposed codes perform very well over additive white Gaussian noise (AWGN) channels.


Author(s):  
Wang Zhongxun ◽  
Sun Ling ◽  
Xi Yang

Recently, Low Density Parity-Check (LDPC) codes based on Affine Permutation Matrices (APM) drew lots of attention. Compared with the Quasi-Cyclic LDPC (QC-LDPC) codes, these kinds of codes have some advantages. APM-LDPC codes obtain lower cycle-distributions, minimum hamming distance and greater girth. This paper explains the importance of cyclic distribution by comparing APM-LDPC codes with QC-LDPC codes. Then a particular form of APM-LDPC codes is proposed and researched. The new codes can low down the cycle-distribution to larger extent. In the following research, an effective method, which constructs the new codes with fixed girth, is proposed. Simulations show that the construction method is reasonable and effective. The transmission performances are better than the traditional methods, as well. Finally, the implementation and verification are carried out on FPGA.


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