Detecting Cycles of Length 8 in the Tanner Graph of a QC-LDPC Code Based on Protograph Analysis

Structured LDPC codes have been constructed using balanced incomplete block (BIB) designs, resolvable BIB designs, mutually orthogonal Latin rectangles, partial geometries, group divisible designs, resolvable group divisible designs and finite geometries. Here we have constructed LDPC codes from α – resolvable BIB and Group divisible designs. The sub–matrices of incidence matrix of such block design are used as a parity – check matrix of the code which satisfy row – column constraint. Here the girth of the proposed code is at least six and the corresponding LDPC code (or Tanner graph) is free of 4– cycles.

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Ruling out small stopping sets and small girth in Tanner graph of QC-LDPC code

Journal of Systems Engineering and Electronics ◽

10.3969/j.issn.1004-4132.2010.01.021 ◽

2010 ◽

Vol 21 (1) ◽

pp. 134-137

Author(s):

Lingjun Kong ◽

Yang Xiao

Keyword(s):

Ldpc Code ◽

Tanner Graph ◽

Stopping Sets

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LDPC code optimization based on Tanner graph mutations

2013 21st Telecommunications Forum Telfor (TELFOR) ◽

10.1109/telfor.2013.6716251 ◽

2013 ◽

Cited By ~ 4

Author(s):

Jan Broulim ◽

Vjaceslav Georgiev ◽

Jan Moldaschl ◽

Lukas Palocko

Keyword(s):

Ldpc Code ◽

Code Optimization ◽

Tanner Graph

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LDPC Codes Based on α – Resolvable BIB and Group Divisible Designs

10.36227/techrxiv.14913171.v1 ◽

2021 ◽

Author(s):

Shyam Saurabh

Keyword(s):

Block Design ◽

Ldpc Codes ◽

Ldpc Code ◽

Finite Geometries ◽

Group Divisible Designs ◽

Tanner Graph ◽

Group Divisible ◽

Check Matrix ◽

Balanced Incomplete Block ◽

Resolvable Group

Structured LDPC codes have been constructed using balanced incomplete block (BIB) designs, resolvable BIB designs, mutually orthogonal Latin rectangles, partial geometries, group divisible designs, resolvable group divisible designs and finite geometries. Here we have constructed LDPC codes from α – resolvable BIB and Group divisible designs. The sub–matrices of incidence matrix of such block design are used as a parity – check matrix of the code which satisfy row – column constraint. Here the girth of the proposed code is at least six and the corresponding LDPC code (or Tanner graph) is free of 4– cycles.

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Investigation of random-structure regular LDPC codes construction based on progressive edge-growth and algorithms for removal of short cycles

Eastern-European Journal of Enterprise Technologies ◽

10.15587/1729-4061.2021.225852 ◽

2021 ◽

Vol 4 (9(112)) ◽

pp. 46-53

Author(s):

Viktor Durcek ◽

Michal Kuba ◽

Milan Dado

Keyword(s):

Hamming Distance ◽

Ldpc Codes ◽

Ldpc Code ◽

Error Correcting Codes ◽

Random Structure ◽

Parity Check ◽

Parity Check Matrix ◽

Tanner Graph ◽

Check Matrix ◽

Computer Based

This paper investigates the construction of random-structure LDPC (low-density parity-check) codes using Progressive Edge-Growth (PEG) algorithm and two proposed algorithms for removing short cycles (CB1 and CB2 algorithm; CB stands for Cycle Break). Progressive Edge-Growth is an algorithm for computer-based design of random-structure LDPC codes, the role of which is to generate a Tanner graph (a bipartite graph, which represents a parity-check matrix of an error-correcting channel code) with as few short cycles as possible. Short cycles, especially the shortest ones with a length of 4 edges, in Tanner graphs of LDPC codes can degrade the performance of their decoding algorithm, because after certain number of decoding iterations, the information sent through its edges is no longer independent. The main contribution of this paper is the unique approach to the process of removing short cycles in the form of CB2 algorithm, which erases edges from the code's parity-check matrix without decreasing the minimum Hamming distance of the code. The two cycle-removing algorithms can be used to improve the error-correcting performance of PEG-generated (or any other) LDPC codes and achieved results are provided. All these algorithms were used to create a PEG LDPC code which rivals the best-known PEG-generated LDPC code with similar parameters provided by one of the founders of LDPC codes. The methods for generating the mentioned error-correcting codes are described along with simulations which compare the error-correcting performance of the original codes generated by the PEG algorithm, the PEG codes processed by either CB1 or CB2 algorithm and also external PEG code published by one of the founders of LDPC codes

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High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding

10.36227/techrxiv.14293508 ◽

2021 ◽

Author(s):

Alireza Hasani ◽

Lukasz Lopacinski ◽

Rolf Kraemer

Keyword(s):

Ldpc Codes ◽

Ldpc Code ◽

Cmos Technology ◽

Low Density ◽

Parity Check ◽

Decoding Algorithm ◽

Chip Area ◽

Tanner Graph ◽

Low Density Parity Check ◽

The One

The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection- based architecture which facilitates the multi-frame decoding of LDPC codes and therefore results in improvement in decoding throughput with bearable hardware overhead. Synthesis in an industrial 28nm CMOS technology shows improved results in terms of throughput, power, and chip area.

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High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding

10.36227/techrxiv.14293508.v1 ◽

2021 ◽

Author(s):

Alireza Hasani ◽

Lukasz Lopacinski ◽

Rolf Kraemer

Keyword(s):

Ldpc Codes ◽

Ldpc Code ◽

Cmos Technology ◽

Low Density ◽

Parity Check ◽

Decoding Algorithm ◽

Chip Area ◽

Tanner Graph ◽

Low Density Parity Check ◽

The One

The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection- based architecture which facilitates the multi-frame decoding of LDPC codes and therefore results in improvement in decoding throughput with bearable hardware overhead. Synthesis in an industrial 28nm CMOS technology shows improved results in terms of throughput, power, and chip area.

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