scholarly journals High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding

2021 ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Ldpc Codes ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Chip Area ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
The One

<p>The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection- based architecture which facilitates the multi-frame decoding of LDPC codes and therefore results in improvement in decoding throughput with bearable hardware overhead. Synthesis in an industrial 28nm CMOS technology shows improved results in terms of throughput, power, and chip area.</p>

scholarly journals High-Throughput Multi-Frame Decoding of QC-LDPC Codes with Modified Rejection-Based Minimum Finding

2021 ◽  
Author(s):  
Alireza Hasani ◽  
Lukasz Lopacinski ◽  
Rolf Kraemer
Keyword(s):  
Ldpc Codes ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Chip Area ◽  
Tanner Graph ◽  
Low Density Parity Check ◽  
The One

<p>The key computation in the min-sum decoding algorithm of a Low-Density Parity-Check (LDPC) code is finding the first two minima and also the location of the first minimum among a set of messages passed from Variable Nodes (VNs) to Check Nodes (CNs) in a Tanner graph. In this paper, we propose a modified rejection-based scheme for this task which is able to find the one-hot sequence of the minimum location instead of its index. We show that this modification effectively reduces the complexity of min-sum decoding algorithm. Additionally, we reveal a pipelining potential in such a rejection- based architecture which facilitates the multi-frame decoding of LDPC codes and therefore results in improvement in decoding throughput with bearable hardware overhead. Synthesis in an industrial 28nm CMOS technology shows improved results in terms of throughput, power, and chip area.</p>

scholarly journals Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm

2018 ◽  
Vol 7 (03) ◽  
pp. 23781-23784
Author(s):  
Rajarshini Mishra
Keyword(s):  
Variance Estimation ◽  
Cyclic Codes ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Low Density ◽  
Parity Check ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Xilinx Fpga

Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

scholarly journals On Analyzing LDPC Codes over Multiantenna MC-CDMA System

2014 ◽  
Vol 2014 ◽  
pp. 1-6
Author(s):  
S. Suresh Kumar ◽  
M. Rajaram
Keyword(s):  
Communication Systems ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Cdma System ◽  
Low Density ◽  
Parity Check ◽  
Simple Method ◽  
Broadband Wireless ◽  
Low Density Parity Check ◽  
Code Division Multiple

Multiantenna multicarrier code-division multiple access (MC-CDMA) technique has been attracting much attention for designing future broadband wireless systems. In addition, low-density parity-check (LDPC) code, a promising near-optimal error correction code, is also being widely considered in next generation communication systems. In this paper, we propose a simple method to construct a regular quasicyclic low-density parity-check (QC-LDPC) code to improve the transmission performance over the precoded MC-CDMA system with limited feedback. Simulation results show that the coding gain of the proposed QC-LDPC codes is larger than that of the Reed-Solomon codes, and the performance of the multiantenna MC-CDMA system can be greatly improved by these QC-LDPC codes when the data rate is high.

A Soft-Input Soft-Output Decoding Algorithm for LDPC Codes Based on Euclidean Distance

2011 ◽  
Vol 63-64 ◽  
pp. 999-1004
Keyword(s):  
Euclidean Distance ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Extended Form ◽  
Decoding Algorithm ◽  
Low Density Parity Check ◽  
Parity Check Codes

Paper has been removed due to plagiarism. The original paper was in an extended form in: Published in IET Communications, Vol 5, Issue 16, pp 2364-2370, 2011 Received on 23rd November 2010 Revised on 21st April 2011 doi: 10.1049/iet-com.2010.1040 Euclidean distance soft-input soft-output decoding algorithm for low-density parity-check codes P.G. Farrell1, L.J. Arnone, J. Castineira Moreira

scholarly journals Hardwarearchitektur für einen universellen LDPC Decoder

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer
Keyword(s):  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Wird Eine ◽  
Ldpc Decoder ◽  
Low Density Parity Check

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

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