This paper describes the algorithm principle of CRC-32 codes, and then proposes multiple bits parallel input to achieve CRC-32 checksum on the basis of the principle. To design modules using VHDL language in Quartus II environment based on Altera’s EP4SGX230KF40C2 chip. Compared to traditional method of serial and 8 bits parallel data input, implementation of the program integrates 16, 32 and 64 bits parallel data input modes, the user can select the appropriate modules according to their needs and environmental constraints, which will greatly enhance the ability to adapt to the system and meet the needs of a variety of environments.
