Efficient Hardware Implementation of Ultralightweight RFID Mutual Authentication Protocol

Security and privacy are the two major concerns of radio-frequency identification (RFID) based identification systems. Several researchers have proposed ultralightweight mutual authentication protocols (UMAPs) to ensure the security of the low cost RFID tags in recent years. However, almost all of the previously proposed protocols have some serious security flaws and are vulnerable to various security attacks (full disclosure attack, desynchronization attack, impersonation attack, etc.). Recently, a more sophisticated and robust UMAP: Robust confidentiality integrity and authentication (RCIA)1 [U. Mujahid, M. Najam-ul-Islam and M. Ali Shami, RCIA: A new ultralightweight RFID authentication protocol using recursive hash, Int. J. Distrib. Sens. Netw. 2015 (2015) 642180] has been proposed. A new ultralightweight primitive, “recursive hash” has been used extensively in the protocol design which provides hamming weight unpredictability and irreversibility to ensure optimal security. In addition to security and privacy, small chip area is another design constraint which is mandatory requirement for a protocol to be considered as ultralightweight authentication protocol. Keeping in view the scenario presented above, this paper presents the efficient hardware implementation of the RCIA for EPC-C1G2 tags. Both the FPGA and ASIC implementation flows have been adopted. The FPGA design flow is primarily used to validate the functionality of the proposed hardware design whereas ASIC design (using TSMC 0.35 μm library) is used to validate the gate count. To the best of our knowledge, this is the first FPGA and ASIC implementation of any ultralightweight RFID authentication protocol. The simulation and synthesis results of the proposed optimal hardware architecture show the compatibility of the RCIA with extremely low cost RFID tags.