Efficient adaptive voltage scaling system through on-chip critical path emulation

Author(s):  
Mohamed Elgebaly ◽  
Manoj Sachdev
2012 ◽  
Vol 8 (1) ◽  
pp. 95-112 ◽  
Author(s):  
Julien De Vos ◽  
Denis Flandre ◽  
David Bol
Keyword(s):  

Author(s):  
Motoi Ichihashi ◽  
Helene Lhermet ◽  
Edith Beigne ◽  
Frederic Rothan ◽  
Marc Belleville ◽  
...  

2010 ◽  
Vol 19 (07) ◽  
pp. 1543-1557
Author(s):  
WEI HU ◽  
TIANZHOU CHEN ◽  
QINGSONG SHI ◽  
SHA LIU

Multithreaded programming has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors. The performance bottleneck of a multithreaded program is its critical path, whose length is its total execution time. As the number of cores within a processor increases, Network-on-Chip (NoC) has been proposed as a promising approach for inter-core communication. In order to optimize the performance of a multithreaded program running on an NoC based multi-core platform, we design and implement the critical-path driven router, which prioritizes inter-thread communication on the critical path when routing packets. The experimental results show that the critical-path driven router improves the execution time of the test case by 14.8% compared to the ordinary router.


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