CRITICAL-PATH DRIVEN ROUTERS FOR ON-CHIP NETWORKS

WEI HU; TIANZHOU CHEN; QINGSONG SHI; SHA LIU

doi:10.1142/s021812661000689x

CRITICAL-PATH DRIVEN ROUTERS FOR ON-CHIP NETWORKS

Journal of Circuits System and Computers ◽

10.1142/s021812661000689x ◽

2010 ◽

Vol 19 (07) ◽

pp. 1543-1557

Author(s):

WEI HU ◽

TIANZHOU CHEN ◽

QINGSONG SHI ◽

SHA LIU

Keyword(s):

Computer Architecture ◽

Execution Time ◽

Critical Path ◽

Network On Chip ◽

Test Case ◽

Total Execution Time ◽

Multithreaded Programming ◽

Multithreaded Program ◽

On Chip ◽

Dominant Paradigm

Multithreaded programming has become the dominant paradigm in computer architecture, mainly in the form of multi-core processors. The performance bottleneck of a multithreaded program is its critical path, whose length is its total execution time. As the number of cores within a processor increases, Network-on-Chip (NoC) has been proposed as a promising approach for inter-core communication. In order to optimize the performance of a multithreaded program running on an NoC based multi-core platform, we design and implement the critical-path driven router, which prioritizes inter-thread communication on the critical path when routing packets. The experimental results show that the critical-path driven router improves the execution time of the test case by 14.8% compared to the ordinary router.

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A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

International Journal of Reconfigurable Computing ◽

10.1155/2011/295385 ◽

2011 ◽

Vol 2011 ◽

pp. 1-15 ◽

Cited By ~ 7

Author(s):

Onur Derin ◽

Erkan Diken ◽

Leandro Fiorin

Keyword(s):

Fault Tolerance ◽

Open Source ◽

Execution Time ◽

Initial Step ◽

Network On Chip ◽

Distributed Model ◽

Total Execution Time ◽

Process Networks ◽

Kahn Process ◽

On Chip

Kahn process networks (KPNs) is a distributed model of computation used for describing systems where streams of data are transformed by processes executing in sequence or parallel. Autonomous processes communicate through unbounded FIFO channels in absence of a global scheduler. In this work, we propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC). We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment) framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

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Research on Network-on-Chip Dynamic and Adaptive Algorithm and Choice Strategy

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.539.296 ◽

2014 ◽

Vol 539 ◽

pp. 296-302

Author(s):

Dong Li

Keyword(s):

Energy Consumption ◽

Execution Time ◽

Adaptive Algorithm ◽

Network On Chip ◽

Time Dimension ◽

Choice Strategy ◽

Bus Structure ◽

On Chip ◽

Mapping Scheme ◽

Single Objective

With further increase of the number of on-chip device, the bus structure has not met the requirements. In order to make better communication between each part, the chip designers need to explore a new structure to solve the interconnection of on-chip device. The paper proposes a network-on-chip dynamic and adaptive algorithm which selects NoC platform with 2-dimension mesh as the carrier, incorporates communication energy consumption and delay into unified cost function and uses ant colony optimization to realize NOC map facing energy consumption and delay. The experiment indicates that compared with random map, single objective optimization can separately saves (30%~47 %) and ( 20%~39%) in communication energy consumption and execution time compared with random map, and joint objective optimization can further excavate the potential of time dimension in mapping scheme dominated by the energy.

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Multi-Core Architecture and Network on Chip: Applications and Challenges

Journal of Computational and Theoretical Nanoscience ◽

10.1166/jctn.2020.8657 ◽

2020 ◽

Vol 17 (1) ◽

pp. 239-245

Author(s):

Maddula N. V. Sesha Saiteja ◽

K. Sai Sumanth Reddy ◽

D. Radha ◽

Minal Moharir

Keyword(s):

Computer Architecture ◽

Network On Chip ◽

Single Chip ◽

Computing Technology ◽

Core Technology ◽

Multiple Cores ◽

Research Problems ◽

On Chip ◽

Many Core ◽

Day By Day

Technology improves performance and reduces in size day by day. Reduction in size can increase the density and which in turn can improve the performance. These statements suit very well for the computer architecture improvement. The whole System on Chip (SoC) brought the concept of multiple cores on a single chip. The multi-core or many-core architectures are the future of computing. Technology has improved in reducing the size and increasing the density, but improving the performance to an expectation of including more cores is a challenge of many-core technology. Utilization of all cores and improving the performance of execution by these cores are the challenges to be addressed in a many-core technology. This paper discusses the basics of many core architecture, comparison and applications. Further, it covers the basics of Network on Chip (NoC), architectural components, and various views of current Network on Chip research problems. Research problems include improving the performance of communication by avoiding congested path in routing.

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