Performance evaluation of on-chip interconnect IP using CBR traffic generator model

2009 ◽  
Author(s):  
Kee Beom Kim ◽  
Seong Min Jo ◽  
Jin Woo Song ◽  
Ki-Seok Chung ◽  
Yong Ho Song
Keyword(s):  
Performance Evaluation ◽  
Generator Model ◽  
Traffic Generator ◽  
On Chip

scholarly journals A Network Traffic Generator Model for Fast Network-on-Chip Simulation

2005 ◽  
Author(s):  
S. Mahadevan ◽  
F. Angiolini ◽  
M. Storgaard ◽  
R.G. Olsen ◽  
J. Sparso ◽  
...  
Keyword(s):  
Network Traffic ◽  
Network On Chip ◽  
Generator Model ◽  
Traffic Generator ◽  
Fast Network ◽  
On Chip

scholarly journals A Network Traffic Generator Model for Fast Network-on-Chip Simulation

2008 ◽  
pp. 173-184 ◽  
Author(s):  
Shankar Mahadevan ◽  
Federico Angiolini ◽  
Jens Sparsø ◽  
Michael Storgaard ◽  
Jan Madsen ◽  
...  
Keyword(s):  
Network Traffic ◽  
Network On Chip ◽  
Generator Model ◽  
Traffic Generator ◽  
Fast Network ◽  
On Chip

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip

2012 ◽  
Author(s):  
Praveen Salihundam ◽  
Mohammed Asadullah Khan ◽  
Shailendra Jain ◽  
Yatin Hoskote ◽  
Satish Yada ◽  
...  
Keyword(s):  
Network On Chip ◽  
Core Network ◽  
Traffic Generator ◽  
On Chip
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