Proceedings of the 8th International Workshop on Interconnection Network Architecture On-Chip, Multi-Chip - INA-OCMC '14

Proceedings of the Fifth International Workshop on Interconnection Network Architecture On-Chip, Multi-Chip - INA-OCMC '11

10.1145/1930037 ◽

2011 ◽

Keyword(s):

Network Architecture ◽

Interconnection Network ◽

International Workshop ◽

On Chip

Proceedings of the 2012 Interconnection Network Architecture on On-Chip, Multi-Chip Workshop - INA-OCMC '12

10.1145/2107763 ◽

2012 ◽

Keyword(s):

Network Architecture ◽

Interconnection Network ◽

On Chip

A novel asymmetric optical interconnection network architecture for network-on-chip

2009 IEEE International Conference on Network Infrastructure and Digital Content ◽

10.1109/icnidc.2009.5360898 ◽

2009 ◽

Author(s):

Huimin Zhang ◽

Yaojun Qiao ◽

Yuefeng Ji

Keyword(s):

Network Architecture ◽

Interconnection Network ◽

Network On Chip ◽

Optical Interconnection ◽

On Chip

2015 Ninth International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip

10.1109/ina-ocmc36085.2015 ◽

2015 ◽

Keyword(s):

Interconnection Network ◽

International Workshop ◽

Network Architectures ◽

On Chip

Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip on - IMA-OCMC '13

10.1145/2482759 ◽

2013 ◽

Keyword(s):

Network Architecture ◽

Interconnection Network ◽

On Chip

Nanophotonic Optical Interconnection Network Architecture for On-Chip and Off-Chip Communications

10.1109/ofc.2008.4528127 ◽

2008 ◽

Cited By ~ 19

Author(s):

Howard Wang ◽

Michele Petracca ◽

Aleksandr Biberman ◽

Benjamin G. Lee ◽

Luca P. Carloni ◽

...

Keyword(s):

Network Architecture ◽

Interconnection Network ◽

Optical Interconnection ◽

On Chip

Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support

Euro-Par 2006 Parallel Processing - Lecture Notes in Computer Science ◽

10.1007/11823285_93 ◽

2006 ◽

pp. 884-895 ◽

Cited By ~ 3

Author(s):

A. Martínez ◽

P. J. García ◽

F. J. Alfaro ◽

J. L. Sánchez ◽

J. Flich ◽

...

Keyword(s):

Network Architecture ◽

Interconnection Network ◽

Cost Effective ◽

Congestion Management ◽

Management Support

Level Based Routing Using Dynamic Programming for 2D Mesh

Cybernetics and Information Technologies ◽

10.1515/cait-2017-0017 ◽

2017 ◽

Vol 17 (2) ◽

pp. 73-82 ◽

Cited By ~ 3

Author(s):

Akash Punhani ◽

Pardeep Kumar ◽

Nitin Nitin

Keyword(s):

Dynamic Programming ◽

Interconnection Network ◽

Routing Algorithm ◽

Networks On Chip ◽

Mesh Topology ◽

On Chip

Abstract The performance of the interconnection network doesn’t only depend on the topology, but it also depends on the Routing algorithm used. The simplest Routing algorithm for the mesh topology in networks on chip is the XY Routing algorithm. The level based Routing algorithm has been proved to be more efficient than the XY Routing algorithm. In this paper, level based Routing algorithm using the dynamic programming has been proposed. The proposed Routing algorithm proves to be more efficient in the terms of the computation. The proposed Routing algorithm has achieved up to two times bigger speed.

Proceedings of the 14th International Workshop on Network on Chip Architectures

10.1145/3477231 ◽

2021 ◽

Keyword(s):

International Workshop ◽

Network On Chip ◽

On Chip

A High Efficient On-Chip Interconnection Network in SIMD CMPs

Algorithms and Architectures for Parallel Processing - Lecture Notes in Computer Science ◽

10.1007/978-3-642-13119-6_13 ◽

2010 ◽

pp. 149-162 ◽

Cited By ~ 3

Author(s):

Dan Wu ◽

Kui Dai ◽

Xuecheng Zou ◽

Jinli Rao ◽

Pan Chen

Keyword(s):

Interconnection Network ◽

High Efficient ◽

On Chip