A novel asymmetric optical interconnection network architecture for network-on-chip

2009 ◽  
Author(s):  
Huimin Zhang ◽  
Yaojun Qiao ◽  
Yuefeng Ji
Keyword(s):  
Network Architecture ◽  
Interconnection Network ◽  
Network On Chip ◽  
Optical Interconnection ◽  
On Chip

Nanophotonic Optical Interconnection Network Architecture for On-Chip and Off-Chip Communications

2008 ◽  
Author(s):  
Howard Wang ◽  
Michele Petracca ◽  
Aleksandr Biberman ◽  
Benjamin G. Lee ◽  
Luca P. Carloni ◽  
...  
Keyword(s):  
Network Architecture ◽  
Interconnection Network ◽  
Optical Interconnection ◽  
On Chip

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

2014 ◽  
Vol 24 (02) ◽  
pp. 1540006 ◽  
Author(s):  
M. M. Hafizur Rahman ◽  
Rizal Mohd Nor ◽  
Tengku Mohd Bin Tengku Sembok ◽  
M. A. H. Akhand
Keyword(s):  
Mesh Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Average Distance ◽  
Small Diameter ◽  
Network On Chip ◽  
Mesh Network ◽  
Minimal Distance ◽  
Bisection Width ◽  
On Chip

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

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