A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip

IEICE Transactions on Information and Systems ◽

10.1587/transinf.2016pap0026 ◽

2016 ◽

Vol E99.D (12) ◽

pp. 2881-2890

Author(s):

Yuan HE ◽

Masaaki KONDO ◽

Takashi NAKADA ◽

Hiroshi SASAKI ◽

Shinobu MIWA ◽

...

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

Runtime Optimization ◽

Selection Framework ◽

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Energy-efficient optical broadcast for nanophotonic networks-on-chip

2012 Optical Interconnects Conference ◽

10.1109/oic.2012.6224445 ◽

2012 ◽

Author(s):

Cheng Li ◽

Mark Browning ◽

Paul V. Gratz ◽

Samuel Palermo

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

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Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2018.00020 ◽

2018 ◽

Author(s):

Somayeh Kashi ◽

Ahmad Patooghy ◽

Dara Rahmati ◽

Mahdi Fazeli ◽

Michel A. Kinsy

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

Efficient Approach ◽

On Chip ◽

Application Specific

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Energy-Efficient Networks-on-Chip Architectures: Design and Run-Time Optimization

Network-on-Chip Security and Privacy ◽

10.1007/978-3-030-69131-8_3 ◽

2021 ◽

pp. 55-75

Author(s):

Sumit K. Mandal ◽

Anish Krishnakumar ◽

Umit Y. Ogras

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

Time Optimization ◽

Run Time ◽

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Tools and methodologies for designing energy-efficient photonic networks-on-chip for highperformance chip multiprocessors

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5537792 ◽

2010 ◽

Author(s):

Johnnie Chan ◽

Gilbert Hendry ◽

Aleksandr Biberman ◽

Keren Bergman

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

Photonic Networks ◽

Networks On Chip ◽

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Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642624 ◽

2010 ◽

Author(s):

Amit Berman ◽

Ran Ginosar ◽

Idit Keidar

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

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Physical synthesis of energy-efficient networks-on-chip through topology exploration and wire style optimization

2005 International Conference on Computer Design ◽

10.1109/iccd.2005.84 ◽

2006 ◽

Author(s):

Yuanfang Hu ◽

Hongyu Chen ◽

Yi Zhu ◽

A.A. Chien ◽

Chung-Kuan Cheng

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

Physical Synthesis ◽

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Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip

Journal of Computer Science and Technology ◽

10.1007/s11390-013-1312-x ◽

2013 ◽

Vol 28 (1) ◽

pp. 54-71 ◽

Author(s):

Xiao-Hang Wang ◽

Peng Liu ◽

Mei Yang ◽

Maurizio Palesi ◽

Ying-Tao Jiang ◽

...

Keyword(s):

Energy Efficient ◽

Networks On Chip ◽

Run Time ◽

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LORAX: Loss-Aware Approximations for Energy-Efficient Silicon Photonic Networks-on-Chip

Proceedings of the 2020 on Great Lakes Symposium on VLSI ◽

10.1145/3386263.3406919 ◽

2020 ◽

Author(s):

Febin Sunny ◽

Asif Mirza ◽

Ishan Thakkar ◽

Sudeep Pasricha ◽

Mahdi Nikdast

Keyword(s):

Energy Efficient ◽

Photonic Networks ◽

Networks On Chip ◽

Silicon Photonic ◽

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Energy-efficient and sustainable communication in optical networks on chip

Sustainable Computing Informatics and Systems ◽

10.1016/j.suscom.2020.100426 ◽

2020 ◽

Vol 28 ◽

pp. 100426

Author(s):

Kapil Sharma ◽

Vivek Kumar Sehgal

Keyword(s):

Optical Networks ◽

Energy Efficient ◽

Networks On Chip ◽

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Fly-Over: A Light-Weight Distributed Power-Gating Mechanism for Energy-Efficient Networks-on-Chip

2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS) ◽

10.1109/ipdps.2017.77 ◽

2017 ◽

Author(s):

Rahul Boyapati ◽

Jiayi Huang ◽

Ningyuan Wang ◽

Kyung Hoon Kim ◽

Ki Hwan Yum ◽

...

Keyword(s):

Energy Efficient ◽

Light Weight ◽

Power Gating ◽

Distributed Power ◽

Networks On Chip ◽

Gating Mechanism ◽

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