2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip
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9781424464692

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4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642688 ◽

2010 ◽

Cited By ~ 9

Author(s):

Nazrul Anuar ◽

Yasuhiro Takahashi ◽

Toshikazu Sekine

Keyword(s):

Two Phase

A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642592 ◽

2010 ◽

Cited By ~ 1

Author(s):

C. Benkeser ◽

A. Bubenhofer ◽

Q. Huang

Keyword(s):

Baseband Receiver ◽

Digital Baseband

Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642689 ◽

2010 ◽

Cited By ~ 1

Author(s):

Tsung-Yi Ho ◽

Sheng-Hung Liu

Keyword(s):

Standard Cell ◽

Cell Placement

A binary adaptable window SoC architecture for a stereo vision based depth field processor

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642626 ◽

2010 ◽

Cited By ~ 8

Author(s):

Andy Motten ◽

Luc Claesen

Keyword(s):

Stereo Vision

Novel ultra low-voltage and high speed domino CMOS logic

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642664 ◽

2010 ◽

Cited By ~ 5

Author(s):

Y. Berg

Keyword(s):

High Speed ◽

Low Voltage

Fine-grained post placement voltage assignment considering level shifter overhead

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642618 ◽

2010 ◽

Cited By ~ 1

Author(s):

Zohreh Karimi ◽

Majid Sarrafzadeh

Keyword(s):

Fine Grained ◽

Level Shifter

A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642628 ◽

2010 ◽

Cited By ~ 5

Author(s):

Mojtaba Valinataj ◽

Siamak Mohammadi

Keyword(s):

Routing Algorithm ◽

Adaptive Routing

An adaptive bilateral motion estimation algorithm and its hardware architecture

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642661 ◽

2010 ◽

Cited By ~ 2

Author(s):

Abdulkadir Akin ◽

Mert Cetin ◽

Burak Erbagci ◽

Ozgur Karakaya ◽

Ilker Hamzaoglu

Keyword(s):

Motion Estimation ◽

Estimation Algorithm ◽

Hardware Architecture ◽

Motion Estimation Algorithm

A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642692 ◽

2010 ◽

Cited By ~ 1

Author(s):

M. Vamshi Krishna ◽

J. Xie ◽

M.A. Do ◽

C.C. Boon ◽

K.S. Yeo ◽

...

Keyword(s):

Ieee 802.15.4 ◽

Frequency Synthesizer ◽

Fully Integrated

Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm)

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2010.5642663 ◽

2010 ◽

Author(s):

Somsubhra Talapatra ◽

Hafizur Rahaman

Keyword(s):

Elliptic Curve ◽

Elliptic Curve Cryptography ◽

Low Complexity ◽

Montgomery Multiplication

2010 18th IEEE/IFIP International Conference on VLSI and System-on-ChipLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS

Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization

A binary adaptable window SoC architecture for a stereo vision based depth field processor

Novel ultra low-voltage and high speed domino CMOS logic

Fine-grained post placement voltage assignment considering level shifter overhead

A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications

An adaptive bilateral motion estimation algorithm and its hardware architecture

A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4

Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm)

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip
Latest Publications