Test Response Compaction in VLSI BIST with Array of Two-Input Linear Logic
2008 ◽
Vol 24
(1-3)
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pp. 235-246
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1996 ◽
Vol 15
(11)
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pp. 1399-1408
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2005 ◽
Vol 22
(6)
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pp. 566-574
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2001 ◽
Vol 32
(4)
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pp. 339-350
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2011 ◽
Vol 30
(10)
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pp. 1534-1544
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