Modified Algorithm for Medium Length Irregular Low Density Parity Check Code with Low Computational Complexity and Error Floor Rate

Proceedings of the 2nd International Symposium on Computer, Communication, Control and Automation ◽

10.2991/3ca-13.2013.89 ◽

2013 ◽

Author(s):

D P Rathod ◽

R N Awale ◽

S V Bonde

Keyword(s):

Computational Complexity ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Computational Complexity ◽

Low Density Parity Check ◽

Medium Length ◽

Modified Algorithm

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An Efficient Genetic Based Algorithm for an Irregular Low Density Parity Check Code with Low Computational Complexity and Low Error Floor

Communications in Computer and Information Science - Advances in Computing, Communication, and Control ◽

10.1007/978-3-642-36321-4_23 ◽

2013 ◽

pp. 249-258

Author(s):

D. P. Rathod ◽

R. N. Awale

Keyword(s):

Computational Complexity ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Computational Complexity ◽

Low Density Parity Check

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An efficient algorithm for irregular Low density Parity Check code with reduced computational complexity and error floor

2012 International Conference on Communication, Information & Computing Technology (ICCICT) ◽

10.1109/iccict.2012.6398190 ◽

2012 ◽

Author(s):

Devichand P. Rathod ◽

Raval N. Awale

Keyword(s):

Computational Complexity ◽

Efficient Algorithm ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check

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An Iterative Scheme for Lowering the Error-Floor of Low-Density Parity-Check Codes

Proceedings of the 2018 International Symposium on Communication Engineering & Computer Science (CECS 2018) ◽

10.2991/cecs-18.2018.19 ◽

2018 ◽

Author(s):

Zuohong Xu ◽

Yanmin Ma ◽

Qian Cheng ◽

Jiang Zhu ◽

Kai Gao

Keyword(s):

Iterative Scheme ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check ◽

Parity Check Codes

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VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity

GLOBECOM '05. IEEE Global Telecommunications Conference, 2005. ◽

10.1109/glocom.2005.1577854 ◽

2005 ◽

Author(s):

Lei Yang ◽

Hui Liu ◽

C.-J.R. Shi

Keyword(s):

Vlsi Implementation ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check ◽

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Novel serial code concatenation strategies for error floor mitigation of low-density parity-check and turbo product codes

Canadian Journal of Electrical and Computer Engineering ◽

10.1109/cjece.2013.6601080 ◽

2013 ◽

Vol 36 (2) ◽

pp. 52-59 ◽

Author(s):

Damian Morero ◽

Mario Hueda

Keyword(s):

Low Density ◽

Parity Check ◽

Error Floor ◽

Product Codes ◽

Low Density Parity Check ◽

Turbo Product Codes

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Field programmable gate array-based investigation of the error floor of low density parity check (LDPC) codes for magnetic recording channel

INTERMAG Asia 2005. Digests of the IEEE International Magnetics Conference, 2005. ◽

10.1109/intmag.2005.1464236 ◽

2005 ◽

Author(s):

Lingyan Sun ◽

Hongwei Song ◽

B.V.K. Vijaya Kumar ◽

Z. Keirn

Keyword(s):

Magnetic Recording ◽

Field Programmable Gate Array ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check ◽

Field Programmable ◽

Recording Channel ◽

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Error Floor Investigation and Girth Optimization for Certain Types of Low-Density Parity Check Codes

Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005. ◽

10.1109/icassp.2005.1415906 ◽

2006 ◽

Author(s):

Lingyan Sun ◽

Hongwei Song ◽

B.V.K. Vijaya-Kumar

Keyword(s):

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check ◽

Parity Check Codes

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Instanton analysis of Low-Density Parity-Check codes in the error-floor regime

2006 IEEE International Symposium on Information Theory ◽

10.1109/isit.2006.261777 ◽

2006 ◽

Author(s):

Mikhail Stepanov ◽

Michael Chertkov

Keyword(s):

Low Density ◽

Parity Check ◽

Error Floor ◽

Low Density Parity Check ◽

Parity Check Codes

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Field-programmable gate-array-based investigation of the error floor of low-density parity check codes for magnetic recording channels

IEEE Transactions on Magnetics ◽

10.1109/tmag.2005.854455 ◽

2005 ◽

Vol 41 (10) ◽

pp. 2983-2985 ◽

Author(s):

Lingyan Sun ◽

Hongwei Song ◽

B.V.K.V. Kumar ◽

Z. Keirn

Keyword(s):

Magnetic Recording ◽

Field Programmable Gate Array ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Magnetic Recording Channels ◽

Low Density Parity Check ◽

Field Programmable ◽

Recording Channels ◽

Parity Check Codes

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Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2005.862074 ◽

2006 ◽

Vol 53 (4) ◽

pp. 892-904 ◽

Author(s):

Lei Yang ◽

Hui Liu ◽

C.-J.R. Shi

Keyword(s):

Fpga Implementation ◽

Low Density ◽

Parity Check ◽

Error Floor ◽

Code Construction ◽

Low Density Parity Check

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