Root Cause Analysis for Pin Leakage

Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

Author(s):  
Jie Zhu ◽  
An Yan Du ◽  
Bing Hai Liu ◽  
Eddie Er ◽  
Si Ping Zhao ◽  
...  

Abstract In this paper, we report an advanced sample preparation methodology using in-situ lift-out FIB and Flipstage for tridirectional TEM failure analysis. A planar-view and two cross-section TEM samples were prepared from the same target. Firstly, a planar-view lamellar parallel to the wafer surface was prepared using in-situ lift-out FIB milling. Upon TEM analysis, the planar sample was further milled in the along-gate and cross-gate directions separately. Eventually, a pillar-like sample containing a single transistor gate was obtained. Using this technique, we are able to analyze the defect from three perpendicular directions and obtain more information on the defect for failure root-cause analysis. A MOSFETs case study is described to demonstrate the procedure and advantages of this technique.


Author(s):  
Jason Wheeler ◽  
John Wolfgong

Abstract The focus of this paper is to present an interesting case study involving Vishay wire-wound (WSC model) resistor failures, which affected a significant number of production and fielded assemblies. The failures were considered “mission critical”, which was the primary driver necessitating root cause analysis. A disciplined approach to the failure analysis effort was established, which resulted in root cause determination and the generation of appropriate corrective actions. This paper will highlight a non-conventional decapsulation method used to preserve the integrity of the fragile resistive element and a “lucky break” that was instrumental in linking the supplier’s actions to the failures.


2010 ◽  
Vol 30 (1) ◽  
pp. 62-65
Author(s):  
Naveed Ramzan ◽  
Shahid Naveed ◽  
Muhammad Rizwan ◽  
Werner Witt

Author(s):  
Y. H. Park ◽  
Michael Cournoyer

The Nuclear Materials Technology (NMT) Division has the largest inventory of glovebox gloves at Los Alamos National Laboratory (LANL). Consequently, the minimization of unplanned breaches of the glove material, typically resulting in glove failures, is a significant safety concern in the daily operations in NMT Division facilities. To investigate processes and procedures that minimize unplanned breaches in the glovebox, information on glovebox glove failures has been compiled from formal records and analyzed using statistical methods. Based on these research results, the next step of the research is to identify root causes of glove failures and the actions adequate to prevent recurrence. In this paper, root cause analysis was conducted for a cleanup breach case study to demonstrate the computerized root cause analysis process. Based on analysis results, effective recommendations were generated.


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