Abdullah A. Hussain CODE DENSITY OPTOMIZATION AND IMPLEMENTATION USING LZW APPROACH BASED ON 32-BIT RISC PROCESSOR

Mapping Intimacies ◽

10.32792/utq/utjsci/vol2/1/14 ◽

2019 ◽

pp. 105-116

Keyword(s):

Risc Processor ◽

Download Full-text

DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.6.4.14864 ◽

2018 ◽

Vol 6 (4) ◽

pp. 38

Author(s):

S. M. BHAGAT ◽

S. U. BHANDARI ◽

◽

Keyword(s):

Download Full-text

FPGA prototyping of a RISC processor core for embedded applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924027 ◽

2001 ◽

Vol 9 (2) ◽

pp. 241-250 ◽

Author(s):

M. Gschwind ◽

V. Salapura ◽

D. Maurer

Keyword(s):

Processor Core ◽

Risc Processor ◽

Embedded Applications

Download Full-text

Design of Efficient Dynamic Scheduling of RISC Processor Instructions

2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) ◽

10.1109/iemcon51383.2020.9284902 ◽

2020 ◽

Author(s):

Anudeep Bonasu ◽

Sushanth Reddy Karmunchi ◽

Nan Wang

Keyword(s):

Dynamic Scheduling ◽

Download Full-text

Efficient Color Space Conversion using Custom Instruction in a RISC Processor

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378204 ◽

2007 ◽

Author(s):

Muhammad Bilal ◽

Shahid Masud

Keyword(s):

Color Space ◽

Custom Instruction ◽

Color Space Conversion ◽

Download Full-text

The simulation of a RISC processor with N.MPC

Proceedings of the 1985 ACM annual conference on The range of computing : mid-80's perspective mid-80's perspective - ACM '85 ◽

10.1145/320435.320512 ◽

1985 ◽

Author(s):

Charles A. Baxley ◽

Frederick A. Zapka

Keyword(s):

Download Full-text

An automated development framework for a RISC processor with reconfigurable instruction set extensions

Proceedings 20th IEEE International Parallel & Distributed Processing Symposium ◽

10.1109/ipdps.2006.1639476 ◽

2006 ◽

Author(s):

N. Vassiliadis ◽

G. Theodoridis ◽

S. Nikolaidis

Keyword(s):

Instruction Set ◽

Development Framework ◽

Risc Processor ◽

Instruction Set Extensions

Download Full-text

Compiler optimizations for code density of variable length instructions

2014 IEEE Workshop on Signal Processing Systems (SiPS) ◽

10.1109/sips.2014.6986074 ◽

2014 ◽

Author(s):

Heikki Kultala ◽

Timo Viitanen ◽

Pekka Jaaskelainen ◽

Janne Helkala ◽

Jarmo Takala

Keyword(s):

Variable Length ◽

Compiler Optimizations ◽

Download Full-text

Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

Frontiers in Neuroscience ◽

10.3389/fnins.2013.00160 ◽

2013 ◽

Vol 7 ◽

Author(s):

Simon Friedmann ◽

Nicolas Frémaux ◽

Johannes Schemmel ◽

Wulfram Gerstner ◽

Karlheinz Meier

Keyword(s):

Download Full-text

A superscalar RISC processor with pseudo vector processing feature

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors ◽

10.1109/iccd.1995.528797 ◽

2002 ◽

Author(s):

K. Shimamura ◽

S. Tanaka ◽

T. Shimomura ◽

T. Hotta ◽

E. Kamada ◽

...

Keyword(s):

Vector Processing ◽

Download Full-text

Design and analysis of the HF-RISC processor targeting voltage scaling applications

2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) ◽

10.1109/sbcci.2016.7724047 ◽

2016 ◽

Author(s):

Felipe Todeschini Bortolon ◽

Sergio Johann Filho ◽

Matheus Gibiluka ◽

Sergio Bampi ◽

Ney Laert Vilar Calazans ◽

...

Keyword(s):

Voltage Scaling ◽

Download Full-text