A superscalar RISC processor with pseudo vector processing feature

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors ◽

10.1109/iccd.1995.528797 ◽

2002 ◽

Author(s):

K. Shimamura ◽

S. Tanaka ◽

T. Shimomura ◽

T. Hotta ◽

E. Kamada ◽

...

Keyword(s):

Vector Processing ◽

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DESIGN AND VERIFICATION OF 16-BIT RISC PROCESSOR USING SYSTEMVERILOG

i-manager s Journal on Circuits and Systems ◽

10.26634/jcir.6.4.14864 ◽

2018 ◽

Vol 6 (4) ◽

pp. 38

Author(s):

S. M. BHAGAT ◽

S. U. BHANDARI ◽

◽

Keyword(s):

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Image filtering by a scaled mean-square-error filter using a vector processing algorithm

Electronics Letters ◽

10.1049/el:19950322 ◽

1995 ◽

Vol 31 (6) ◽

pp. 443-444

Author(s):

L. Guan ◽

X.L. Zhou

Keyword(s):

Mean Square Error ◽

Image Filtering ◽

Processing Algorithm ◽

Mean Square ◽

Vector Processing

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FPGA prototyping of a RISC processor core for embedded applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.924027 ◽

2001 ◽

Vol 9 (2) ◽

pp. 241-250 ◽

Author(s):

M. Gschwind ◽

V. Salapura ◽

D. Maurer

Keyword(s):

Processor Core ◽

Risc Processor ◽

Embedded Applications

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Infrared small target detection based on salient region extraction and gradient vector processing

Proceedings of the 2019 International Conference on Robotics, Intelligent Control and Artificial Intelligence - RICAI 2019 ◽

10.1145/3366194.3366269 ◽

2019 ◽

Author(s):

Junchang Zhang ◽

Bochuan Zhang ◽

Pu Liu

Keyword(s):

Target Detection ◽

Small Target ◽

Gradient Vector ◽

Small Target Detection ◽

Salient Region ◽

Vector Processing ◽

Region Extraction ◽

Infrared Small Target

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Design of Efficient Dynamic Scheduling of RISC Processor Instructions

2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) ◽

10.1109/iemcon51383.2020.9284902 ◽

2020 ◽

Author(s):

Anudeep Bonasu ◽

Sushanth Reddy Karmunchi ◽

Nan Wang

Keyword(s):

Dynamic Scheduling ◽

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Efficient Color Space Conversion using Custom Instruction in a RISC Processor

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378204 ◽

2007 ◽

Author(s):

Muhammad Bilal ◽

Shahid Masud

Keyword(s):

Color Space ◽

Custom Instruction ◽

Color Space Conversion ◽

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The simulation of a RISC processor with N.MPC

Proceedings of the 1985 ACM annual conference on The range of computing : mid-80's perspective mid-80's perspective - ACM '85 ◽

10.1145/320435.320512 ◽

1985 ◽

Author(s):

Charles A. Baxley ◽

Frederick A. Zapka

Keyword(s):

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An automated development framework for a RISC processor with reconfigurable instruction set extensions

Proceedings 20th IEEE International Parallel & Distributed Processing Symposium ◽

10.1109/ipdps.2006.1639476 ◽

2006 ◽

Author(s):

N. Vassiliadis ◽

G. Theodoridis ◽

S. Nikolaidis

Keyword(s):

Instruction Set ◽

Development Framework ◽

Risc Processor ◽

Instruction Set Extensions

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Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate

Frontiers in Neuroscience ◽

10.3389/fnins.2013.00160 ◽

2013 ◽

Vol 7 ◽

Author(s):

Simon Friedmann ◽

Nicolas Frémaux ◽

Johannes Schemmel ◽

Wulfram Gerstner ◽

Karlheinz Meier

Keyword(s):

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Design and analysis of the HF-RISC processor targeting voltage scaling applications

2016 29th Symposium on Integrated Circuits and Systems Design (SBCCI) ◽

10.1109/sbcci.2016.7724047 ◽

2016 ◽

Author(s):

Felipe Todeschini Bortolon ◽

Sergio Johann Filho ◽

Matheus Gibiluka ◽

Sergio Bampi ◽

Ney Laert Vilar Calazans ◽

...

Keyword(s):

Voltage Scaling ◽

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