PROGRAMMING METHOD OF THE MDR32F9Q2I MICROCONTROLLER IN CONTROL AND MONITORING TASKS

Разработана методика, обеспечивающая полный спектр организации работ по программированию микроконтроллера MDR32F9Q2I, которая позволяет получить, в частности, системы управления и мониторинга источников вторичного электроснабжения. Программирование микроконтроллера, построенного на базе высокопроизводительного процессорного RISC ядра ARM, производилось в интегрированной среде разработки Eclipse IDE в операционной системе Windows 10 Pro. Интегрированная среда разработки Eclipse выбрана как наиболее удобная и доступная среда, поддерживает всевозможные типы языков программирования и непрерывную компиляцию. В настоящее время 16- и 32-битные микроконтроллеры быстро набирают популярность в сфере промышленных задач. Их применение обусловлено постоянно возрастающей сложностью задач, жесткими требованиями к производительности интегрируемых контроллеров управления, необходимостью иметь в электронных устройствах развитые органы пользовательского управления. Представленный стенд для моделирования, использующий интерфейсный мост между шинами I2C и 1-Wire - DS2482-100, преобразует протоколы между управляющим I2C микроконтроллером (мастером) и ведомыми 1-Wire устройствами, а также контролирует скорости нарастания и уменьшения напряжения в линии. Основой для написания класса DS2482 являются заголовочные файлы Arduino.h и OneWire.h, которые находятся в свободном доступе In this article, we developed a technique that provides a full range of organization of works on programming the MDR32F9Q2I microcontroller, which allows you to obtain control and monitoring systems for secondary power supply sources. The microcontroller based on the high-performance ARM RISC processor core was programmed in the Eclipse IDE on the Windows 10 Pro operating system. We chose the Eclipse integrated development environment as the most convenient and accessible environment, it supports all kinds of programming languages and continuous compilation. Currently, 16- and 32-bit microcontrollers are rapidly gaining popularity in the field of industrial tasks. Their use is due to the ever-increasing complexity of tasks, stringent requirements for the performance of integrated controllers, the need to have advanced user controls in electronic devices. We present a simulation stand that uses an interface bridge between the I2C and 1-Wire buses - DS2482-100, converts protocols between the I2C microcontroller (master) and 1-Wire slaves, and also controls the voltage rise and fall rates in the line. The basis for writing the DS2482 class is the Arduino.h and OneWire.h header files, which are freely available

FPGA configuration of an alloyed correlated branch predictor used with RISC processor for educational purposes

Instructions pipelining is one of the most outstanding techniques used in improving processor speed; nonetheless, these pipelined stages are constantly facing stalls that caused by nested conditional branches. During the execution of nested conditional branches, the behavior of the running branch depends on the history information of the previous ones; therefore, these branches have the greatest effect in reducing the prediction accuracy of a branch predictor among conditional branches. The purpose of this research is to reduce the stall cycles caused by correlated branches misprediction by introducing a hardware model of a branch predictor that combines both local and global prediction techniques. This predictor integrates the prediction characteristics of the alloyed predictor with those of the correlated predictor. the predictor design which implemented in VHDL (Very high-speed IC hardware description language) was inserted in previously designed MIPS (microprocessor without interlocked pipelined stages) processor and its prediction accuracy was confirmed by executing a program using the selection sort algorithm to sort 100 input numbers of different combinations ascendingly.

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.