Near-threshold Computing and Performance Optimization of MOS Current Mode Logic Circuits

2014 ◽  
Vol 13 (6) ◽  
pp. 1216-1221
Author(s):  
Jianping Hu ◽  
Kaiyu Zou
Keyword(s):  
Performance Optimization ◽  
Current Mode ◽  
Logic Circuits ◽  
Current Mode Logic ◽  
And Performance ◽  
Near Threshold

3.3-V BiCMOS current-mode logic circuits for high-speed adders

1996 ◽  
Vol 31 (8) ◽  
pp. 1165-1169 ◽  
Author(s):  
A. Bellaouar ◽  
H. Touzene
Keyword(s):  
High Speed ◽  
Current Mode ◽  
Logic Circuits ◽  
Current Mode Logic

scholarly journals Cross-Layer Reliability, Energy Efficiency, and Performance Optimization of Near-Threshold Data Paths

2020 ◽  
Vol 10 (4) ◽  
pp. 42
Author(s):  
Mehdi Tahoori ◽  
Mohammad Saber Golanbari
Keyword(s):  
Energy Efficiency ◽  
Performance Optimization ◽  
Supply Voltage ◽  
Cross Layer ◽  
Improve Energy Efficiency ◽  
Threshold Data ◽  
Order Of Magnitude ◽  
Improved Performance ◽  
And Performance ◽  
Near Threshold

Modern electronic devices are an indispensable part of our everyday life. A major enabler for such integration is the exponential increase of the computation capabilities as well as the drastic improvement in the energy efficiency over the last 50 years, commonly known as Moore’s law. In this regard, the demand for energy-efficient digital circuits, especially for application domains such as the Internet of Things (IoT), has faced an enormous growth. Since the power consumption of a circuit highly depends on the supply voltage, aggressive supply voltage scaling to the near-threshold voltage region, also known as Near-Threshold Computing (NTC), is an effective way of increasing the energy efficiency of a circuit by an order of magnitude. However, NTC comes with specific challenges with respect to performance and reliability, which mandates new sets of design techniques to fully harness its potential. While techniques merely focused at one abstraction level, in particular circuit-level design, can have limited benefits, cross-layer approaches result in far better optimizations. This paper presents instruction multi-cycling and functional unit partitioning methods to improve energy efficiency and resiliency of functional units. The proposed methods significantly improve the circuit timing, and at the same time considerably limit leakage energy, by employing a combination of cross-layer techniques based on circuit redesign and code replacement techniques. Simulation results show that the proposed methods improve performance and energy efficiency of an Arithmetic Logic Unit by 19% and 43%, respectively. Furthermore, the improved performance of the optimized circuits can be traded to improving the reliability.

Power-gating Schemes of MOS Current Mode Logic Circuits for Power-down Applications

2014 ◽  
Vol 13 (3) ◽  
pp. 515-521
Author(s):  
Kaiyu Zou ◽  
Jianping Hu ◽  
Dan Yang
Keyword(s):  
Current Mode ◽  
Logic Circuits ◽  
Power Gating ◽  
Current Mode Logic
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